* Minor Scaladoc update
 - add/move package descriptive text
 - fix FixedPoint link (it's chisel3.experimental.FixedPoint)

* Add missing period at EOS

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

* Move Aggregate, Clock, Mem, Printf, Reg

* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

* Revive core package object to provide aliases for moved definitions.

* Cleanup package definitions; eliminate ambiguous implicits

* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

* Put BitPat back in chisel3.util

* More experimental motion - avoid multiple import definitions.

* Add experimental.FixedPoint alias

* Add EnumType definition to core package.
Update deprecated messages to refer to correct object

* Move FixedPoint into the experimental package (but keep it in Bits.scala).

* Add missing implicits to core/package - compatibility

* Cleanup: update ScalaDoc references; remove unused imports

* Add Reset alias to core/package

* Use common 3.2...

* RawModule with no reset should be able to use withClock method.
- refactor ClockAndReset
  - now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params
  - convenience methods clock and reset tries to deref the option
  - ClockAndReset.empty is factory method for (None, None)
- In Builder
  - forcedClock does not check resetOpt now
  - forcedReset does not check clockOpt now
- withClock no longer looks at resetOpt
- withReset no longer looks at clockOpt
- Module starts with empty ClockAndReset

* RawModule with no reset should be able to use withClock method.
Refactor again based on @ducky64 comments
- refactor away ClockAndReset, now builder just has a
  - currentClock
  - currentReset
- withClock, withRest, withClockAndReset just use these fields directly

* RawModule with no reset should be able to use withClock method.
- Fixed typo in withReset handler, now picks up new reset

Miscellaneous Scaladoc Cleanup

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This moves the documentation for loadMemoryFromFile onto the object as
opposed to the apply method. This includes additional cleanup in terms
of fixing uses of "$", topical grammar/capitalization, and adding more
outbound links.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This removes uses of @usecase. This is deprecated in Scala 2.13.x.
Additionally, scala generious spurious warnings if you use @usecase in
a non-abstract class. (It thinks that this is an abstract member of
something concrete.)

The guidance from upstream Scala is to be explicit about how to use
your API via @example.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This uses the `-sourcepath` and `-doc-source-url` options when
generating Scaladoc in add a link to the Chisel3 GitHub source file.
This is setup to link to master if a "-SNAPSHOT" version is used. If
the documentation is built for a non-snapshot version, then this will
use the "v$version" branch on GitHub.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Change LFSR16 deprecation from 3.3 -> 3.2

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state

Changes the internal state of PRNG to use Vec[Bool] instead of UInt.
This fixes an @aswaterman identified future problem with asynchronous
reset.

A register with an asynchronous reset can only be reset to a literal.
Previously, an LFSR would store state as a UInt. If it was not
parameterized with a seed it should have its least significant bit
reset to something to avoid locking up. It's ideal to not reset the
full UInt (better test coverage, decreased reset fanout). However,
it's difficult to only reset one bit of a UInt. Conversely, it's
trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR
closer to a canonical representation of their internal state, i.e.,
it's natural to think of generalizing Vec[Bool] to arbitrary finite
fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2.

Minor updates:

- Updates/fixes to some scaladoc
- Add assertion to period test to make sure LFSR is changing

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* IO(Analog) fixed for RawModule

* Add a Analog Port for RawModule test & spec

* Fixes around Module instantiation and ports in AnalogPortRawModuleTest

* Shorten Comment

* Add Data.isSynthesizable to distinguish SampleElementBinding

This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)

* Fix pretty printing for Vec

* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog

- Add chisel3.util.random package with Galois and Fibonacci LFSRs
- Add maximal period LFSR generation and maximal period taps
- Deprecate chisel3.util.LFSR16 in favor of chisel3.util.random.LFSR(16)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Add LFSR tests using LFSR16 testing infrastructure. This also adds
tests that are the same as the examples shown for LFSR scaladoc.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Builds out PRNG and LFSR type hierarchy. PRNG is the base class of
LFSR of which Galois and Fibonacci are concrete implementations.

PRNGs contain state (a UInt) and an update (delta) function. They have
a compile-time optional seed to set the PRNG state. The seed/state can
also be set at run-time. PRNGs can be run-time parameterized based on
how many updates they should do per cycle and whether or not to send
the seed through step-count state updates before loading it. (h/t
@jwright6323)

LFSRs are parameterized in a reduction operation (XOR or XNOR). An
LFSR that does NOT have a seed will be automatically initialized to a
minimally safe state (set/reset one bit) based on their reduction
operation. (h/t @aswaterman)

Adds Galois and Fibonacci LFSRs that define appropriate update
functions. Companion objects provide helpers to automatically generate
maximal period variants. Taps are provide for a very large set of
widths. The LFSR companion object provides an apply method to generate
a Fibonacci LFSR random variable (like the old LFSR16).

Make LFSR testing generic to enable it to test other LFSRs.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Closes #1075.

This is necessary to support code that imports an implicit conversion
from Int to UInt

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063

This causes sbt tasks (run, test, etc.) to fork to a separate JVM to
avoid running out of metaspace. This issue crops up for developers or
users repeatedly running sbt tasks in the same sbt session.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

- Introduce internal helper `castToInt`, which issues an error when the input
BigInt can't be represented as Int.

- Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.

Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.