- May 13, 2019
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Schuyler Eldridge authored
This adds the following FIRRTL Annotations to Chisel: - NoRunFirrtlCompilerAnnotation - PrintFullStackTraceAnnotation - ChiselGeneratorAnnotation - ChiselCircuitAnnotation - ChiselOutputFileAnnotation This includes tests for ChiselGeneratorAnnotation as this Annotation is able to be constructed from a String and to elaborate itself. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- May 11, 2019
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Schuyler Eldridge authored
Change LFSR16 deprecation from 3.3 -> 3.2
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Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- May 10, 2019
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Andrew Waterman authored
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Andrew Waterman authored
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Schuyler Eldridge authored
LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state
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Schuyler Eldridge authored
Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Jack Koenig authored
* IO(Analog) fixed for RawModule * Add a Analog Port for RawModule test & spec * Fixes around Module instantiation and ports in AnalogPortRawModuleTest * Shorten Comment * Add Data.isSynthesizable to distinguish SampleElementBinding This helps clarify the notion of being bound but not hardware. Data.topBindingOpt is now used to get the *actual* top binding, including across SampleElements (eg. in Analog checking that the top is bound to a Port or a Wire) * Fix pretty printing for Vec * Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
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Schuyler Eldridge authored
- Add chisel3.util.random package with Galois and Fibonacci LFSRs - Add maximal period LFSR generation and maximal period taps - Deprecate chisel3.util.LFSR16 in favor of chisel3.util.random.LFSR(16)
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Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Schuyler Eldridge authored
Add LFSR tests using LFSR16 testing infrastructure. This also adds tests that are the same as the examples shown for LFSR scaladoc. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Schuyler Eldridge authored
Builds out PRNG and LFSR type hierarchy. PRNG is the base class of LFSR of which Galois and Fibonacci are concrete implementations. PRNGs contain state (a UInt) and an update (delta) function. They have a compile-time optional seed to set the PRNG state. The seed/state can also be set at run-time. PRNGs can be run-time parameterized based on how many updates they should do per cycle and whether or not to send the seed through step-count state updates before loading it. (h/t @jwright6323) LFSRs are parameterized in a reduction operation (XOR or XNOR). An LFSR that does NOT have a seed will be automatically initialized to a minimally safe state (set/reset one bit) based on their reduction operation. (h/t @aswaterman) Adds Galois and Fibonacci LFSRs that define appropriate update functions. Companion objects provide helpers to automatically generate maximal period variants. Taps are provide for a very large set of widths. The LFSR companion object provides an apply method to generate a Fibonacci LFSR random variable (like the old LFSR16).
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- May 09, 2019
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Schuyler Eldridge authored
Make LFSR testing generic to enable it to test other LFSRs. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- May 05, 2019
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edwardcwang authored
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- May 02, 2019
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Paul Rigge authored
Closes #1075.
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- Apr 27, 2019
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Richard Lin authored
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- Apr 25, 2019
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Jack Koenig authored
This is necessary to support code that imports an implicit conversion from Int to UInt
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- Apr 24, 2019
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Jack Koenig authored
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- Apr 20, 2019
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Edward Wang authored
Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063
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- Apr 17, 2019
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Schuyler Eldridge authored
This causes sbt tasks (run, test, etc.) to fork to a separate JVM to avoid running out of metaspace. This issue crops up for developers or users repeatedly running sbt tasks in the same sbt session. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Apr 16, 2019
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Andrew Waterman authored
- Introduce internal helper `castToInt`, which issues an error when the input BigInt can't be represented as Int. - Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.
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edwardcwang authored
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- Apr 13, 2019
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Jack Koenig authored
This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf
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- Apr 02, 2019
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Richard Lin authored
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- Mar 30, 2019
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Jack Koenig authored
Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates
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- Mar 29, 2019
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Jim Lawson authored
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
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- Mar 27, 2019
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Jim Lawson authored
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- Mar 26, 2019
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Richard Lin authored
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Richard Lin authored
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- Mar 24, 2019
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Jim Lawson authored
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772.
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Sequencer authored
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- Mar 23, 2019
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Edward Wang authored
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Jack Koenig authored
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Hasan Genc authored
* Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style
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- Mar 22, 2019
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Richard Lin authored
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Richard Lin authored
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- Mar 21, 2019
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Jim Lawson authored
* Replace textual release version with Shields SemVer badge. * Provide useful button action for release badge.
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edwardcwang authored
Co-Authored-By:
Jack Koenig <jack.koenig3@gmail.com> Co-Authored-By:
Jim Lawson <ucbjrl@berkeley.edu>
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- Mar 19, 2019
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Jim Lawson authored
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
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- Mar 16, 2019
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Andrew Waterman authored
Tighten inferred width for PopCount
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