1. Aug 23, 2023
    • Will Dietz's avatar
      ProbeSpec: Add force/release simulator test. (#3501) · d5b79fa2
      Will Dietz authored
      Some limitations for default simulation environment:
      * Verilator's force doesn't update when the RHS changes,
        as documented, so in tests re-force as needed or otherwise
        workaround this limitation.
      * Verilator rejects designs that attempt to force an input port,
        with ASSIGNIN.  Force other signals instead.
      * `forceInitial` does not appear to work (Verilator?),
        the generated Verilog works in VCS.  Workaround.
        (Chisel `forceInitial` -> `initial force the.lhs.target = rhs_value;`)
      d5b79fa2
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