import cleanup AddImplicitOutputAnnotationFile
scaladoc link cleanup in Convert
DriverCompatibility import and scaladoc link cleanup
Elaborate import cleanup
ChiselAnnotations import cleanup
ChiselCli map changed to foreach
ChiselStage import cleanup
package import cleanup

This converts the original chisel3.Driver to use
chisel3.stage.ChiselStage. This is implemented in the following way:

  1. ExecutionOptions are converted to an AnnotationSeq

  2. The AnnotationSeq is preprocessed using phases contained in the
     Chisel DriverCompatibility objects. One of these *disables* the
     execution of FirrtlStage by ChiselStage.
  3. ChiselStage runs on the preprocessed AnnotationSeq
  4. The input ExecutionOptionsManager is mutated based on the output
     of ChiselStage.
  5. The FIRRTL stage is re-enabled if it's supposed to run and
     selected FIRRTL DriverCompatibility phases run.
  6. FirrtlStage runs
  7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult

This modifies the original DriverSpec to make it more verbose with the
addition of info statements. The functionality of the DriverSpec is
unmodified.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds a method to enable conversion from ChiselExecutionOptions back to
an AnnotationSeq.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This includes phases necessary to provide backwards compatibility with
the old Chisel3 Driver. These are placed in a DriverCompatibility
object inside chisel3.stage.phases. The following four phases are
included:
  - AddImplicitOutputFile (from a TopNameAnnotation)
  - AddImplicitOutputAnnotationFile phase
  - DisableFirrtlStage (to disable ChiselStage running FirrtlStage)
  - MutateOptionsManager (to update options after ChiselStage)
  - ReEnableFirrtlStage (to renable FirrtlStage if needed)

Additionally, this adds a view of a ChiselExecutionResult for
providing the legacy return type of the Chisel Driver.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds ChiselStage, a reimplementation of chisel3.Driver as a
firrtl.options.Stage. This is simplistically described as a pipeline
of Phases.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds an Emitter Phase that writes a ChiselCircuitAnnotation to
a file if a ChiselOutputFileAnnotation is present.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This coalesces three distinct operations into one Convert Phase:

  1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
  2. Conversion of Chisel Annotations to FIRRTL Annotations
  3. Generation of RunFirrtlTransformAnnotations

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds an Elaborate Phase that expands ChiselGeneratorAnnotations
into ChiselCircuitAnnotations and deletes the original.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds the following FIRRTL Annotations to Chisel:

- NoRunFirrtlCompilerAnnotation
- PrintFullStackTraceAnnotation
- ChiselGeneratorAnnotation
- ChiselCircuitAnnotation
- ChiselOutputFileAnnotation

This includes tests for ChiselGeneratorAnnotation as this Annotation
is able to be constructed from a String and to elaborate itself.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Change LFSR16 deprecation from 3.3 -> 3.2

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state

Changes the internal state of PRNG to use Vec[Bool] instead of UInt.
This fixes an @aswaterman identified future problem with asynchronous
reset.

A register with an asynchronous reset can only be reset to a literal.
Previously, an LFSR would store state as a UInt. If it was not
parameterized with a seed it should have its least significant bit
reset to something to avoid locking up. It's ideal to not reset the
full UInt (better test coverage, decreased reset fanout). However,
it's difficult to only reset one bit of a UInt. Conversely, it's
trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR
closer to a canonical representation of their internal state, i.e.,
it's natural to think of generalizing Vec[Bool] to arbitrary finite
fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2.

Minor updates:

- Updates/fixes to some scaladoc
- Add assertion to period test to make sure LFSR is changing

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* IO(Analog) fixed for RawModule

* Add a Analog Port for RawModule test & spec

* Fixes around Module instantiation and ports in AnalogPortRawModuleTest

* Shorten Comment

* Add Data.isSynthesizable to distinguish SampleElementBinding

This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)

* Fix pretty printing for Vec

* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog

- Add chisel3.util.random package with Galois and Fibonacci LFSRs
- Add maximal period LFSR generation and maximal period taps
- Deprecate chisel3.util.LFSR16 in favor of chisel3.util.random.LFSR(16)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Add LFSR tests using LFSR16 testing infrastructure. This also adds
tests that are the same as the examples shown for LFSR scaladoc.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Builds out PRNG and LFSR type hierarchy. PRNG is the base class of
LFSR of which Galois and Fibonacci are concrete implementations.

PRNGs contain state (a UInt) and an update (delta) function. They have
a compile-time optional seed to set the PRNG state. The seed/state can
also be set at run-time. PRNGs can be run-time parameterized based on
how many updates they should do per cycle and whether or not to send
the seed through step-count state updates before loading it. (h/t
@jwright6323)

LFSRs are parameterized in a reduction operation (XOR or XNOR). An
LFSR that does NOT have a seed will be automatically initialized to a
minimally safe state (set/reset one bit) based on their reduction
operation. (h/t @aswaterman)

Adds Galois and Fibonacci LFSRs that define appropriate update
functions. Companion objects provide helpers to automatically generate
maximal period variants. Taps are provide for a very large set of
widths. The LFSR companion object provides an apply method to generate
a Fibonacci LFSR random variable (like the old LFSR16).

Make LFSR testing generic to enable it to test other LFSRs.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Closes #1075.

This is necessary to support code that imports an implicit conversion
from Int to UInt

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063

This causes sbt tasks (run, test, etc.) to fork to a separate JVM to
avoid running out of metaspace. This issue crops up for developers or
users repeatedly running sbt tasks in the same sbt session.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

- Introduce internal helper `castToInt`, which issues an error when the input
BigInt can't be represented as Int.

- Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates