Skip to content
GitLab
  1. Aug 28, 2019
  3. Aug 20, 2019
  5. Aug 16, 2019
  7. Aug 14, 2019
  9. Aug 13, 2019
    • Jack Koenig's avatar
      Add support for asynchronous reset (#1011) · 24dddea6
      Jack Koenig authored 
      Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:

  val asyncReset: AsyncReset = IO(Input(AsyncReset()))
  val syncReset: Bool = IO(Input(Bool()))
  val abstractReset: Reset = IO(Input(Reset()))

  val asyncReg = withReset(asyncReset) { RegInit(0.U) }
  val syncReg = withReset(syncReset) { RegInit(0.U) }
  val inferredReg = withReset(abstractReset) { RegInit(0.U) }

AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.

Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.
      24dddea6
    • Adam Izraelevitz's avatar
      Aspect-Oriented Programming for Chisel (#1077) · fddb5943
      Adam Izraelevitz authored 
      Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
      fddb5943
    • Schuyler Eldridge's avatar
      Merge pull request #1151 from colin4124/patch1 · 466ffbc9
      Schuyler Eldridge authored 
      Remove "-Xcheckinit" from build.sc
      466ffbc9
  11. Aug 12, 2019
  13. Aug 09, 2019
  15. Aug 07, 2019
  17. Aug 02, 2019
  19. Aug 01, 2019