- Jan 16, 2021
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Jiuyang liu authored
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Jiuyang liu authored
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Jack Koenig authored
Farewell Scala 2.11
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- Jan 15, 2021
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Jiuyang liu authored
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- Jan 11, 2021
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Megan Wachs authored
* Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget
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- Jan 07, 2021
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Jiuyang Liu authored
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- Dec 18, 2020
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Jack Koenig authored
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Jack Koenig authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Jack Koenig authored
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- Dec 17, 2020
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Jack Koenig authored
MiMa binary compatibility checks are now run on master, but the mimaPreviousArtifacts are empty which makes the check a no-op. This helps keep both the build.sbt and CI more consistent between master and stable branches. .mergify.yml is also updated with mergify.sc from chisel-repo-tools using the following configuration: conditions: - status-success=all tests passed branches: - 3.2.x - 3.3.x - 3.4.x
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- Dec 09, 2020
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Chick Markley authored
- fix build.sbt - fix build.sc
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- Dec 08, 2020
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Jiuyang Liu authored
* Builder: use LazyLogging.logger.warn to print elaboration message * add deprecation for chisel3.internal.ErrorLog.info. * add test to check elaboration message still exist. Co-authored-by:Kevin Laeufer <kevin.laeufer@sifive.com>
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- Dec 02, 2020
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Jack Koenig authored
Implemented by folding Element.ref into Data.ref. Element.ref had special handling for literals, but because Bundles can also be literals, there were code paths that tried to get the ref of a Bundle literal which was non-existent. Now, all literals are handled together. Because FIRRTL does not have support for Bundle literals, Bundle literal refs are implemented by materializing a Wire.
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Kevin Laeufer authored
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- Nov 24, 2020
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Jack Koenig authored
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- Nov 17, 2020
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Daniel Kasza authored
* Improve source locators for switch statements.
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- Nov 12, 2020
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Jack Koenig authored
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- Nov 11, 2020
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Jack Koenig authored
The SecurityManager is global so is not thread-safe. This is the source of flaky tests in FIRRTL CI. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Jack Koenig authored
* Refine autonaming to have more intuitive behavior Last name in an Expression wins, while the first Statement to name wins. This is done via checking the _id of HasIds during autonaming and only applying a name if the HasId was created in the scope of autonaming. There is no change to .autoSeed or .suggestName behavior. Behavior of chisel3-plugins from before this change is maintained. * Update docs with naming plugin changes
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- Nov 06, 2020
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Jack Koenig authored
This is a refinement of the assertion added in #1616 then removed in #1654. Because Records now set the refs of children upon binding, later, unbound Records could incorrectly override the refs. The first set should win.
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- Nov 04, 2020
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Jack Koenig authored
It causes issues for some legal (if awkward) patterns. A larger refactor of when refs are set could reinstate this check.
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- Nov 03, 2020
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John Ingalls authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Adam Izraelevitz authored
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- Oct 31, 2020
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Jack Koenig authored
This requires a combination of things, but it happens to be a combination used by Diplomacy in Rocket Chip. It must be a Record in compatibility code with Vecs as fields and a mix of components with and without set directions.
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- Oct 28, 2020
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Adam Izraelevitz authored
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- Oct 27, 2020
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Adam Izraelevitz authored
* Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Adam Izraelevitz authored
* Bugfix - module name collision for injecting aspect * Fixed mechanism to avoid module name collisions * Added comments for reviewer feedback Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Adam Izraelevitz authored
* Added forcename transform and tests * Added documentation and additional error checking * Added mdoc. Added RunFirrtlTransform trait * Removed TODO comment * Addressed reviewer feedback * Removed trailing comma Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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PENGUINLIONG authored
Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Adam Izraelevitz authored
Causes issues when building the website, using these docs. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Oct 23, 2020
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Jack Koenig authored
* Use Data refs for name prefixing with aggregate elements Vecs set the refs of their elements upon construction of those elements. In the past, Records haven't set their elements refs until module close, but it can be done sooner. Doing it upon binding means that refs will at least be available for Records used in hardware elements. Since only bound Data can be connected to anyway, Aggregate elements being connected to will always have a ref which we can then use for creating naming prefixes. * Add tighter correctness checks * Handle more cases in connection prefixing Add support for forcing setRef to override a previous setting. This is only used by BlackBox ports which need to drop their io prefix. Also add a Try() around Data.bindingToString which sometimes throws exceptions when being used to .toString a Data in an error message. * Strip trailing spaces in names in compiler plugin
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- Oct 22, 2020
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Schuyler Eldridge authored
* Fix `-e` option causing ChiselStage.emit* to error Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of `-e` ChiselStage behavior Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add test of `-e` ChiselStage behavior
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- Oct 20, 2020
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Jack Koenig authored
This allows for sharing of the prefix stacks between Data, and removes a boxing per prefix stack element that is no longer necessary. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Schuyler Eldridge authored
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Oct 15, 2020
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Jack Koenig authored
Package chisel3 was not properly marked as an internal package so source locators in reported errors would point to files like Bits.scala.
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- Oct 14, 2020
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Chick Markley authored
* ExtModule's lacked support built in support for providing the verilog source. This changes creates traits that can be used with ExtModule to provide the support currently found in BlackBox - Add support for ExtModule helpers - HasExtModuleResource to use addResource - HasExtModuleInline to use setInline - HasExtModulePath to use addPath - Add tests of the above support. - Note: These tests use Stage instead of Driver - Added ScalaDoc for HasBlackBoxInline#setInline * Fix the danged trailing commas. * Change to use `.transform` as the correct API for `ChiselStage`
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- Oct 13, 2020
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Jack Koenig authored
Fixes #1606 Previously, the Data itself would be put on the prefix stack and its full name would be used as the prefix for subsequent names. This meant that prefixes would grow quadratically as the prefix is present both on the Data pushed to the stack, and on the stack itself. This is fixed by just using the "local" name of the Data being pushed on the stack. A related issue is deferring the name resolution. This led to unintuitive behavior when the name of a Data used as a prefix is overridden later (usually when the Data is a return value). The overriding name would show up in prefixes twice instead of once. It is much more intuitive to grab the name at the moment of the connection creating the prefix rather than deferring to later. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Oct 12, 2020
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Jack Koenig authored
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- Oct 06, 2020
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Adam Izraelevitz authored
* Fix broken mdoc * Added test-chisel-docs to ci workflow * Add requirement on build-treadle job * Added forgotton colon * Forgot cd into chisel3 dir * moved three docs into explanations * Updated reference Co-authored-by:Schuyler Eldridge <schuyler.eldridge@gmail.com>
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