Properties can be fields of Bundles and used in wires.

add Path property type

Fix ExtModules to not silently drop Property IO.

This is half of #3509.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add Map properties

This is an automated commit generated by Chisel's CD flow.

Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Fix an issue where the release notes would generate a URL like:

    [text]("url")

Change this to the following by using the `jq` raw string option:

    [text](url)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Properties in package chisel3.ltl will now be clocked and disabled by
default (if there is an implicit clock and disable). Default disable is
not hasBeenReset of the current implicit reset (if one exists). The
clock and disable can be removed by setting them to None via withClock,
withReset, and withDisable APIs.

Change the time that the CIRCT nightly runs from 0800 UTC to 1000 UTC.
This increase the staggering between the upstream llvm/circt nightly
artifact job from a 1-hour delay to a 3-hour delay (start time to start
time).  The upstream llvm/circt nightly artifact job is now longer (~2.5
hours) as it builds full CIRCT w/ shared libs as opposed to just firtool.

This avoids a "bug" where the Chisel/CIRCT nightly would run before the
CIRCT artifact nightly finished causing the former to use the previous
night's nightly.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* add HasChisel trait

* remove tail spaces

* add ChiselCIRCTPanamaBinderModule

* add bindertest in build system

* Implement PanamaCIRCTConverter

* [ci] Run simple tests for PanamaCIRCTConverter

---------

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

This reverts commit cddedd24.

Fix nightly CIRCT builds.  The binary name changed from "firrtl-" to
"firtool-".

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Some limitations for default simulation environment:
* Verilator's force doesn't update when the RHS changes,
  as documented, so in tests re-force as needed or otherwise
  workaround this limitation.
* Verilator rejects designs that attempt to force an input port,
  with ASSIGNIN.  Force other signals instead.
* `forceInitial` does not appear to work (Verilator?),
  the generated Verilog works in VCS.  Workaround.
  (Chisel `forceInitial` -> `initial force the.lhs.target = rhs_value;`)

* withClock, withReset, and withClockAndReset now have forms that take
  Option[Clock] and Option[Reset]
* Module.clockOption and Module.resetOption return Option[Clock] and
  Option[Reset]

Change the printing of the CIRCT version to show up in the
GITHUB_STEP_SUMMARY.  This makes it easier to know what version CIRCT ran
with, particularly for a nightly run.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Classes can only be elaborated with Definition. Instantiation via D/I is
not yet supported--current instantiation is via an unsafe "by name" API.

This includes the API, Chisel IR, Converter, FIRRTL IR, and Serializer
support for Seqs of Properties (and Property of Seq). This includes
support for values are Seqs of Properties which themselves may or may
not be literals.

This includes support for Property[String] and literals.

This includes the API, Chisel IR, Converter, FIRRTL IR, and Serializer
support for Property literals.

* [dependencies] Fix incorrect Trace test
* [cd] Bump CIRCT from firtool-1.48.0 to firtool-1.50.0

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This includes the API, Chisel IR, Converter, FIRRTL IR, and Serializer
support for Property connections.

It also includes moving requireVisible from Data to BaseType, which is
required but was omitted from #3442.

Add a CD (continuous delivery) GitHub action that will automatically
create PRs that bump CIRCT to the latest version.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>