nitpick

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Using https://github.com/ucb-bar/chisel-repo-tools/pull/31

* Remove space between backticks and language
* Make code examples in memories explanation work

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add documentation guide about memory initialization

* Move information to experimental and add ref

* Add CCC2021 info

* Update README.md

* Update README.md

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Update the FAQ and add doc on versioning
* Update modules.md

Co-authored-by: Megan Wachs <megan@sifive.com>

Updates to chisel3 documentation for website:
* guard code examples with mdoc and fix errors encountered along the way
* move some website content here vs splitting the content across two repos
* Bring in the interval-types and loading memories content so that it will be visible from the website
* remove all references to the wiki (deprecated)
* Remove reference to Wiki from the README
* fix tabbing and compile of chisel3-vs-chisel2 section
* Appendix: faqs now guarded and compile
* FAQs: move to resources section

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Change top.cpp to deassert reset one time unit before the clock asserts.
This avoids a Verilator simultation issue in top.cpp where the eval()
function is only called once per simultation loop.  If the clock and
reset are both changed and eval() is only called once, then any
combinational update due to a change in reset is not visible to the
sequential logic.  This avoids issues where the downstream compilation
utilities move synchronous reset logic outside of an always block that
describes a synchronous reset flip flop.

Reset now deasserts on time unit 10 and the clock ticks on time unit
11.

h/t @albert-magyar

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change a test to use emitChirrtl instead of emitFirrtl. This test
isn't supposed to be running the Scala FIRRTL Compiler, but the latter
method causes this to happen.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Compiler plugin implemented autoclonetype

The compiler plugin obviates the need for using stack traces to
determine outer objects in autoclonetype. When the plugin was used to
compile a given Bundle, it will no longer collect a stack trace upon
construction. This should have massive benefits to elaboration runtime.

This annotation adds memory import with inline generation for the
emmiter.
Supports both readmemh and readmemb statements based on argument.

* Adding ChiselEnum Documentation Entry

Added documentation for the ChiselEnum type with verified examples

* Fixed some doc ambiguity and repeated emitVerilog calls

* Added ChiselStage and commented out package definition since packages cannot be declared in single files

* Fixed issue with ChiselStage not being able to generate a module with parameters and bad package imports

* Opps on not adding _ after import

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Modified Bundle for ci and made changes to select naming scheme

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Added missing backticks

* Added space around error block quote

* Fixed md paragraph in code

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Fixed some comments and formatting

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Not a Pokémon

* Handle MemTypeBinding in Analog

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix stack trace trimming across ChiselStage

Fix bug in stack trace trimming behavior. Now, the following is what
happens:

1. The Builder, if catching accumulated errors, will now throw a
   ChiselException with a Scala-trimmed Stack trace. Previously, this
   would throw the full excpetion.
2. The Elaborate phase handles stack trace trimming. By default, any
   Throwable thrown during elaboration will have its stack
   trace *mutably* trimmed and is rethrown. A logger.error is printed
   stating that there was an error during elaboration and how the user
   can turn on the full stack trace. If the --full-stacktrace option
   is on, then the Throwable is not caught and only the first
   logger.error (saying that elaboration failed) will be printed.
3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain
   all inherit the behavior of (2).

Mutable stack trace trimming behavior is moved into an implicit
class (previously this was defined on ChiselException only) so this
can be applied to any Throwable.

No StageErrors are now thrown anymore. However, StageErrors may still
be caught by ChiselMain (since it is a StageMain).

Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test
all this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Make Data GC-able

No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.

* Add MemTypeBinding for port types of Mems

This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.

* Call _onModuleClose on unbound Records

This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.

This is a new SBT build unit that symlinks in some files from the normal
chisel project tests, but builds them without the compiler plugin.

* Added SyncReadMem-based implementation of the Queue class

* Rework of the parametrized Queue class SyncReadMem-based implementation

* Modification of the parametrized Queue class SyncReadMem-based implementation

* Limiting the visibility of the read address for SyncReadMem-based Queue

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>

* Fix some botched formatting (replace ```mdoc scala with ```scala mdoc)
* Replace some unnecessary uses of triple backticks with single
  backticks
* Move appendix docs from wiki-deprecated/ to appendix/
  * This will require an update on the website as well
* Update Bundle literal docs

* Update reported width from div/rem to match FIRRTL results

* Add tests for width of % and / on UInt and SInt

* Add loop-based test for known UInt/SInt op result widths

Co-authored-by: Jack Koenig <koenig@sifive.com>

If a method passed to higher function does not return any value,
it is prefer to use `foreach` instead of `map`.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>