- Sep 01, 2015
- Aug 29, 2015
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azidar authored
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- Aug 27, 2015
- Aug 26, 2015
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Andrew Waterman authored
Code like add(UInt<1>(1), SInt<1>(1)) was resulting in Verilog like $signed(1'h1) + $signed(1'sh1) which is incorrect: it computes -2, not 0. The fix is to zero-extend the unsigned operand, e.g. $signed({1'b0,1'h1}) + $signed(1'sh1) -
azidar authored
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azidar authored
Removed IntWidth, now only use LongWidth. Now do width inference for Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
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azidar authored
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- Aug 25, 2015
- Aug 21, 2015
- Aug 20, 2015
- Aug 19, 2015
- Aug 18, 2015
- Aug 06, 2015
- Aug 05, 2015
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azidar authored
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