Code like

    add(UInt<1>(1), SInt<1>(1))

was resulting in Verilog like

    $signed(1'h1) + $signed(1'sh1)

which is incorrect: it computes -2, not 0.  The fix is to zero-extend the
unsigned operand, e.g.

    $signed({1'b0,1'h1}) + $signed(1'sh1)

Removed IntWidth, now only use LongWidth. Now do width inference for Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt

Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.

Updated tests to match. #29.

an optimization that eliminated some when statements.

Added test case.