Fix Verilog backend for mixed signed-unsigned ops

Code like

    add(UInt<1>(1), SInt<1>(1))

was resulting in Verilog like

    $signed(1'h1) + $signed(1'sh1)

which is incorrect: it computes -2, not 0.  The fix is to zero-extend the
unsigned operand, e.g.

    $signed({1'b0,1'h1}) + $signed(1'sh1)