- Dec 10, 2021
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mergify[bot] authored
* catch None.get in BitPat.apply(x: UInt): BitPat (#2276) Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 849d4a0b ) # Conflicts: # src/test/scala/chiselTests/util/BitPatSpec.scala * Resolve backport conflicts Remove BitPatSpec since this backport is just a simple require. Co-authored-by:
Jiuyang Liu <liu@jiuyang.me> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Aug 31, 2021
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mergify[bot] authored
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source. (cherry picked from commit 7fb2c1eb ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
(cherry picked from commit 29665743 ) Co-authored-by:
Kevin Laeufer <laeufer@cs.berkeley.edu>
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- Aug 30, 2021
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mergify[bot] authored
(cherry picked from commit 0a985f7d ) Co-authored-by:
Megan Wachs <megan@sifive.com>
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- Jul 10, 2021
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mergify[bot] authored
* Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031) PR #2023 fixed a composition issue for chisel3 biconnects delegating to FIRRTL partial connect when compatibility mode Bundles are elements of chisel3 Bundles. It missed an important case though that caused previously working code to break. The bug is fixed by doing the automatic flipping for compatibility mode Bundles that have "Input" as a direction in addition to those that are "Flipped". (cherry picked from commit 5183ef88 ) # Conflicts: # src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala * Resolve backport conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jul 09, 2021
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mergify[bot] authored
* Make it legal for concrete resets to drive abstract reset (#2018) This has been legal in FIRRTL since v1.2.3 (when reset inference started using a unification-style algorithm) but was never exposed in the Chisel API. Also delete the overridden connects in AsyncReset and ResetType which just duplicate logic from MonoConnect. (cherry picked from commit 4b7b771e ) * Fix issues with tests Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023) BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a Bundle defined in `import Chisel._`. Because chisel3 <> is commutative it needs to be mindful of flippedness when emitting a FIRRTL <- (which is *not* commutative). (cherry picked from commit 16c0b53e ) * Fix test issue in Scala 2.11 Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 30, 2021
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mergify[bot] authored
* Restore aop.Select behavior for CloneModuleAsRecord (cherry picked from commit 0531cb53) * Change behavior of aop.Select to not include CloneModuleAsRecord Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs. (cherry picked from commit 25a84b56 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Fix CloneModuleAsRecord support for .toTarget (cherry picked from commit d3e13ce2) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/RawModule.scala # core/src/main/scala/chisel3/internal/Builder.scala # core/src/main/scala/chisel3/internal/firrtl/Converter.scala * Set refs for ModuleClone and ClonePorts in less hacky way (cherry picked from commit b87107ad ) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/RawModule.scala * Fixup for backport * Resolve merge conflicts * Fix semantic meaning change of Module -> MultiIOModule on master * Waive bincompat errors that cannot impact Scala users Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- May 26, 2021
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Jiuyang Liu authored
This reverts commit 2f938c7e.
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- May 20, 2021
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mergify[bot] authored
* Implement PLA (#1912) * implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by:
Boyang Han <yqszxx@gmail.com> (cherry picked from commit 1c1a4d72 ) * fix 2.11 Co-authored-by:
Jiuyang Liu <liu@jiuyang.me>
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- Mar 30, 2021
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mergify[bot] authored
(cherry picked from commit 9c9bc131 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Mar 19, 2021
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mergify[bot] authored
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit ac094a5e ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Feb 24, 2021
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mergify[bot] authored
Not a Pokémon (cherry picked from commit c2ba4098 ) Co-authored-by:
edwardcwang <edwardcwang@users.noreply.github.com>
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- Feb 06, 2021
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mergify[bot] authored
Signed-off-by:
Jean Bruant <jean.bruant@ovhcloud.com> (cherry picked from commit e3b6cf4e ) Co-authored-by:
John's Brew <46595442+johnsbrew@users.noreply.github.com>
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- Feb 02, 2021
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mergify[bot] authored
* Update reported width from div/rem to match FIRRTL results * Add tests for width of % and / on UInt and SInt * Add loop-based test for known UInt/SInt op result widths Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 98ce9194 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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- Jan 27, 2021
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mergify[bot] authored
If a method passed to higher function does not return any value, it is prefer to use `foreach` instead of `map`. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 654db98e ) Co-authored-by:
SoyaOhnishi <ohnishi.soya@arc.cs.okayama-u.ac.jp>
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mergify[bot] authored
(cherry picked from commit d0db0b8b ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jan 25, 2021
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mergify[bot] authored
This is a nit fix. no logic is changed. * Rename `typeName` to `enumTypeName` in ScalaDoc * Add return type at public method * Rename `enum_records` into `enumRecords` to retain name consistency Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 2a967670 ) Co-authored-by:
SoyaOhnishi <ohnishi.soya@arc.cs.okayama-u.ac.jp>
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- Jan 12, 2021
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mergify[bot] authored
Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (bp #1714) (#1720) * Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (#1714) * Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget (cherry picked from commit b578aa5e ) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * fixup! Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (#1714) Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Dec 18, 2020
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Jack Koenig authored
(cherry picked from commit a600a95b)
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mergify[bot] authored
* Remove CircleCI (#1702) Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit eae69e95 ) # Conflicts: # .circleci/config.yml * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Dec 17, 2020
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mergify[bot] authored
* Switch to using Github Actions CI (#1690) MiMa binary compatibility checks are now run on master, but the mimaPreviousArtifacts are empty which makes the check a no-op. This helps keep both the build.sbt and CI more consistent between master and stable branches. .mergify.yml is also updated with mergify.sc from chisel-repo-tools using the following configuration: conditions: - status-success=all tests passed branches: - 3.2.x - 3.3.x - 3.4.x (cherry picked from commit 25a417f8 ) # Conflicts: # .mergify.yml # build.sbt # project/plugins.sbt * Resolve merge conflicts * Remove mdoc check from GithubActions This test was added in 3.4 Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 11, 2020
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mergify[bot] authored
* Provide user source locators in Builder.error errors (#1618) Package chisel3 was not properly marked as an internal package so source locators in reported errors would point to files like Bits.scala. (cherry picked from commit baea2da8 ) * Resolve backport issues Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Support using switch without importing SwitchContext (#1595) (cherry picked from commit 9c4f14fb ) # Conflicts: # docs/src/wiki-deprecated/cookbook.md * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Ignore tests using System.setSecurityManager (#1661) The SecurityManager is global so is not thread-safe. This is the source of flaky tests in FIRRTL CI. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 9f1d6cbb ) # Conflicts: # src/test/scala/chiselTests/stage/ChiselStageSpec.scala * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 20, 2020
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mergify[bot] authored
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit ac641fb1 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Oct 10, 2020
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Jack Koenig authored
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- Sep 10, 2020
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mergify[bot] authored
* fix loadMemoryFromFile to work with binary Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation * Added test for binary format support in loadMemoryFromFile * Added test for binary format support in loadMemoryFromFile (cherry picked from commit 88265eec ) Co-authored-by:
HappyQuark <54497326+HappyQuark@users.noreply.github.com>
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- Aug 07, 2020
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mergify[bot] authored
comment fix only. (cherry picked from commit f13b29d1 ) Co-authored-by:
Leigang Kou <56602048+leikou01@users.noreply.github.com>
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- Jul 31, 2020
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mergify[bot] authored
* Added broken auto-clonetype test * Added bugfix for 2.11 * Add descriptive comment for 2.11 special case * Update src/test/scala/chiselTests/AutoClonetypeSpec.scala * Update src/test/scala/chiselTests/AutoClonetypeSpec.scala Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 3b206b50 ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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- Jul 29, 2020
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mergify[bot] authored
(cherry picked from commit a4312eb0 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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- Jun 24, 2020
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mergify[bot] authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit a1edc8f4 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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mergify[bot] authored
* Add containsCause exception search testing util * Use ChiselStage in Tests * Remove Driver usage in Emitter * Remove Driver usage in ChiselSpec * Remove Driver usage from Chisel._ package * Deprecate Driver Execution classes * Code simplification in internal Chisel._ method * Clarify chiselTests.Utils.extractCause Scaladoc Co-authored-by:
Chick Markley <chick@qrhino.com> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jun 23, 2020
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mergify[bot] authored
* Canonicalize construction of empty Decoupled * Change signature after dev meeting discussion * Make EmptyBundle private and final * Add test case for Decoupled with no payload * Apply suggestions from code review Co-authored-by:
Richard Lin <richard.lin@berkeley.edu> Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
Richard Lin <richard.lin@berkeley.edu> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 28e1a244 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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Jack Koenig authored
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mergify[bot] authored
* Closes #1385 Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 1692b8a1 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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- Jun 20, 2020
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mergify[bot] authored
(cherry picked from commit 9bda7a75 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 09, 2020
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mergify[bot] authored
* Immediately throw Builder.error errors outside hardware context * Add example of hidden no-hardware-context error from #1422 Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 99ac8a13 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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mergify[bot] authored
* Added group chisel API * Removed println * Added scaladoc * Added more tests * Cleaned spacing and removed println Co-authored-by:
Chick Markley <chick@qrhino.com> Co-authored-by:
Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 161938b8 ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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