Update reported width from div/rem to match FIRRTL results (#1748) (#1769) (bbd62b2f) · Commits · github.com / freechipsproject / chisel3

Unverified Commit bbd62b2f authored Feb 01, 2021 by

mergify[bot] Committed by GitHub Feb 01, 2021

Update reported width from div/rem to match FIRRTL results (#1748) (#1769)



* Update reported width from div/rem to match FIRRTL results

* Add tests for width of % and / on UInt and SInt

* Add loop-based test for known UInt/SInt op result widths

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 98ce9194

)

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

parent a9002b07

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