This annotation is being handled in mfc via:
  https://github.com/llvm/circt/pull/4665

The convention lets users define how ports with aggregate types are
lowered to verilog.

This PR cleaned up the old build script, split it to common.sc and
builds.sc two files. common.sc is used for declare the dependencies and
project structual for each modules, which can be reused by other
projects for building from source. build.sc is used for build project in
tree.
This commit makes chisel3[2.13.10] able to compile.

Also switch from Mill's BuildInfo to our own

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* the firtool version is now included in the BuildInfo
* firtool now must be on the path when publishing, but is not required
  for building or testing
* FirtoolNonZeroExitCode now no longer includes a stack trace

Add new workflow to generate release notes. This workflow can be run
manually via workflow dispatch, but will also run automatically upon
creating a release. The workflow dispatch can be used for testing,
previewing release notes for a potential release, or for generating
release notes for past releases for when the automation has a bug or
didn't exist.

Also update the PR template and CONTRIBUTING guidelines to include
information about the new required labels and automation. Also
streamline the PR template a little bit to nudge developers towards
putting more information in the "Release Notes" section of the PR
template.

This extends the set of circt intrinsics with Chisel wrappers. These have no impact on code not using them.

Remove the _compatAutoWrapPorts method as this does nothing.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Previously, the naming plugin would not recurse for the RHS of an
unapply, meaning that vals declared in blocks that ultimately return
some result that is unapplied into some named Data would not be named.

Also, audit and improve the naming mdocs.

* Added definition identifiers

A definition identifier is an eager, descriptive name that we can give module definitions. This is to help apply box-typing more generally in Chisel.

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Implement `typeName` API for a few `Data` types

* Fix silly compilation error

* Implement typeName API further for most data types and modules which need it

* Compilation error fixes

* Remove width parameter from Bool

* Test for Queue naming using typeNames

* Remove width-sensitive override for AsyncReset as it is irrelevant

* Add typeName for Analogs

* Add additional types to be tested

* Scalafmt

* Use circt ChiselStage

* Update queue naming of existing tests

* Scalafmt

* Change pipe desiredName to be consistent with other modules

* Update naming cookbook

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add SInt to TypenameSpec

* Fix cookbook mdoc errors

* compileOnly tag on scala code

* More improvements of mdoc

* compileOnly -> compile-only

* Final mdoc review and fixes

* Add inferred UInt to test

---------

Co-authored-by: Megan Wachs <megan@sifive.com>

Deprecate ChiselStage$.elaborate as this exposes internal Chisel APIs,
namely "chisel3.internal.firrtl.Circuit".  Replace usages of this in
tests with emitCHIRRTL.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Change many tests from simulation-based to checking the CHIRRTL.
* Move tests that were hard to convert to new VecIntegrationSpec in
  integration-tests

Co-authored-by: Jack Koenig <koenig@sifive.com>

* mdoc-ify intrinsic explanation

* Update docs/src/explanations/intrinsics.md

* Update intrinsics.md

* IntModule

* intmodule works

* a bit of documentation

* formatting

* example and better test.  Rename all the things, now they are Blue!

* formatting

* typo

* move file

* indexes

* Update core/src/main/scala/chisel3/internal/firrtl/IR.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/intrinsics.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/intrinsics.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* simplify tests

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Change FIRRTL Circuit conversion/serialization to place
ChiselAnnotations (converted to FIRRTL Annotations) inside the FIRRTL
Circuit and to serialize this using the "%[[]]" inline JSON format that
is present in the FIRRTL spec.  This does not remove _all_ annotations
passed via the annotation file, but it is the first step towards that.

* Add low-level svsim based simulation to Chisel
* Add Peek/Poke API

Introduce `svsim`, a low level library for simulating SystemVerilog using Verilator and VCS. (#3121)

Also run formatting on SBT files.

Directly subclassing Iterable is lazy-ish, but if you call any operation
on the resulting value (eg. map or ++) it will evaluate the Iterable and
return a List.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>