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freechipsproject
chisel3
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mill0p11
ce397ed3
·
add mill to ci
·
Jun 21, 2023
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chisel3p6_buildinfo_fix
391b6f64
·
Update build.sc
·
Jun 21, 2023
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firrtl-desiredname
5a41b6e3
·
Add pipe to the optional string
·
Jun 15, 2023
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mill_migration
0a9fff51
·
fix
·
Jun 16, 2023
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girish_bundle_tap_fix
56ca0286
·
Merge branch 'main' of github.com:chipsalliance/chisel into girish_bundle_tap_fix
·
Jun 14, 2023
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fix-empty-aggregate-width
51bb524d
·
Return 0.U(0.W) from .asUInt on empty Aggregates
·
Jun 13, 2023
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oss-cad-bump
ad9c8d24
·
bumping to 2023-06-12
·
Jun 12, 2023
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mergify/bp/3.6.x/pr-3352
f069cc10
·
Add support for zero-width bit extraction (#3352)
·
Jun 09, 2023
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mergify/bp/3.6.x/pr-3349
7a309f16
·
Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (#3349)
·
Jun 09, 2023
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remove-2.12
8bb247ce
·
clean up mill build.
·
Jun 09, 2023
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jackkoenig/opaque-type-asuint
69138481
·
Make it possible to illegalize .asUInt on OpaqueTypes
·
Jun 08, 2023
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chisel-mem-interface-api
1aeab48a
·
Fix mdocs so it compiles
·
Jun 08, 2023
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dev/seldridge/use-simpler-firrtl-syntax
880969d1
·
fixup! Use new connect/invalidate FIRRTL emission
·
Jun 08, 2023
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bump-scala
d7be4332
·
Bump to newly released Scala 2.13.11 and 2.12.18
·
Jun 06, 2023
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mergify/bp/5.x/pr-3147
6115b0f3
·
Update ChiselRunners to use svsim (#3147)
·
Jun 05, 2023
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jackkoenig/subaccess-node
fbc25de7
·
Create nodes for Vec subaccesses that can be named
·
Jun 02, 2023
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jackkoenig/vec-dynamic-indexing-width-warning-3.6.x-backport
e0d91b61
·
Warn on incorrect widths for Vec dynamic indexing
·
Jun 02, 2023
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tap-interface
5d90d305
·
Merge branch 'main' of github.com:chipsalliance/chisel into tap-interface
·
Jun 01, 2023
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jackkoenig/dataview-enhancements
628d7510
·
Add support for DontCare in DataView targets
·
May 25, 2023
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mergify/bp/5.x/pr-3280
93792464
·
[codegen] Simpler FIRRTL Code for Reg w/o Reset (#3280)
·
May 16, 2023
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