Add preliminary support for RV32Zfh extension

D$: guarantee that no-alloc accesses are ordered even if aliased

Currently, non-allocating accesses can be reordered with allocating
accesses if they are to different virtual synonyms.  Add hardware
to detect and prevent this case.

If there's no possibility of aliasing or non-allocating accesses,
there's no additional HW cost.

I'm not entirely happy with the approach (it adds a lot of fanout to
what is sometimes a critical timing path, so at minimum it's leaky).
Might revisit later.

Subsystem: Add HierarchicalLocation

Mainly to mention that chisel3 and firrtl should only be bumped to
stable branches

Co-authored-by: Megan Wachs <megan@sifive.com>

# Conflicts:
#	firrtl
#	wit-manifest.json

The semantics of a register field with a width = 0 are rather undefined for downstream tools. Are you supposed to define software headers for them? Are you supposed to create documentation for them?

Simplify this confusion by just omitting them from the OM entirely.

add SuperscalarEventSets into Events.scala

add SuperscalarEventSets into Events.scala

Fix various bugs related to the new user bits in TileLink

This got messed up when the original branch was merged with the TileLink
parameters refactor.

User bits overhaul

The bridge behaviour before the introduction of AMBAProt:
APB  pprot = 1	=> priv, secure, !fetch
AHB  hprot = 3	=> priv,         !fetch, !buffer, !cache
AXI4 prot  = 1  => priv, secure, !fetch
AXI4 cache = 0  =>                       !buffer, !cache, !modify

For compliance with this clause in the priv spec:

"The mcause values after reset have implementation-specific interpretation,
but the value 0 should be returned on implementations that do not distinguish
different reset conditions"

* Build AsyncResetSynchronizerShiftReg from new SynchronizerPrimitive

* SyncResetSychronizer: Construct out of single bit shift regs

* ShiftReg: Add comment to distinguish types

* Synchronizers: Refactor how the SynchronizerShiftReg are done internally

* Synchronizers: no longer allow specification of reset value

* Synchronizers: remove some redundant withReset

* Synchronizers: update interrupt crossings to deal with the requirement that async crossings are truly async and marked with SynchronizerPrimitiveShiftReg

* AsyncQueue: only use synchronizers of a fixed depth

* Synchronizers: Add initial values back to the API

* Debug Synchronizers: revert change now that initialization is back in the API

* synchronizers: fix typo in parameter ordering, restore some additional API

* Crossing: deprecate instead of delete the heavily used IntSyncCrossingSink API for asynchronous interrupt crossings

* Synchronizers: fix the postfixing of the primitive

* Allow SynchronizerShiftReg to have a special case of 0 where we just assign out to in

* Allow SyncResetSynchronizerShiftReg to have a special case of 0 where we just assign out to in

* Synchronizer: don't touch the ports so that the primitive I/O is predictable even when data is constant

* travis: bump to python3-pexpect since gdbserver.py was bumped to python3

* Revert "travis: bump to python3-pexpect since gdbserver.py was bumped to python3"

This reverts commit 74ae7576cf643259de3227eacb0ac4f644361be2.

* Synchronizer: workaround for a chisel bug to keep I/O names stable

* Revert "Synchronizer: don't touch the ports so that the primitive I/O is predictable even when data is constant"

This reverts commit a9e83e42222e9ba5e616a408a09123f1fa10a39f.

Co-authored-by: Ryan Macdonald <rmac@sifive.com>

BundleMap: improved API for user bits

Multiplier: Make MultiplierIO clone-able

Support for versioning in diplomacy (old userbits)

BaseSubsystem: Rename attach method and traits