riscv-tests hasn't built or installed the hex files this rule is trying to symlink for years.

This dead code is kind of a wart for a downstream rule in chipyard that also wants to generate this same file (obviously it is easily worked around by just naming it something different).

Convert LazyRoCC examples to use chisel3 syntax instead of legacy Chisel compatibility.

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Teach OM about Zfh extension

a.k.a. minFLen = 16.

Add CreditedIO to support register-register interfacing for AXI4 and TL

RVV 1.0: reorder fields in vtype

https://github.com/riscv/riscv-v-spec/commit/b8cd98bc9467617b6653583116b2dfe9eefb2f51

Add OMVectorExtension.vstartALU field

This describes whether non-memory instructions support nonzero vstart values.

Changed the function called cover to mincover. Tightened the bound for the fragmenter by adding shrinktransfer. Added comment.

Update RVV whole-register load/store opcodes

https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5

change monitor to not put diplomacy in error messages

TileLink Diplomacy parameters supportsProbe -> supports.probe

interrupt-controller@xyz can get pretty long on Sv48 systems.

Add Reset Stretcher in PRCI Domain for async reset systems

Enable ResetAsynchronousFull in IDPool

Tile PRCI Domain Wrappers

prci: clock sources and sinks can have names which are used in their group bundle names instead of indexes