* Priv 1.12: PTW page fault instead of access exception if PTE reserved bit set

* PTE.reserved_for_future

* TLBEntryData.pf ptw_pf_array

* PTWResp gpa_is_pte, now that resp_gf can be set by stage-2 page-fault

Update GroundTest to use generic BuildHellaCache key

* AmbaProt memory type for non-cacheable fetches should be "Normal Non-cacheable Bufferable"

* Fix HPROT[3] (cacheable) encoding in TLToAHB bridge

Bump to Chisel 3.5

This PR implements v0.6.2 of the RISC-V Hypervisor Extension.

The implementation was inspired by José Martins' and colleagues' work
described in [1]. Much of the microarchitecture and essentially all of
the code is new, but their implementation served as our baseline.
We thank them for trailblazing hypervisor support in rocket-chip.

Note that this PR only includes the mechanisms to virtualize the hart
itself. Virtualized interrupt controllers, IOMMUs, etc. are future work.
Lots of future work.

Note also that some features are (legally) not implemented. Currently,
misa.H is not writable, something we may or may not choose to fix.
The mtinst and htinst CSRs are hardwired to 0, placing
additional onus on hypervisor software to use the HLVX instruction.

[1] "A First Look at RISC-V Virtualization from an Embedded Systems Perspective", https://arxiv.org/abs/2103.14951



Co-authored-by: John Ingalls <john.ingalls@sifive.com>

* Removed UNMI

* Added new mnie bit to mnstatus

* Fix read value of mnstatus.mpp

Co-authored-by: Ernie Edgar <ernie.edgar@sifive.com>

Bumping hardfloat for fixed .gitmodules.

Bumping torture for https:// riscv-test-env submodule.

Attempt to switch CI from ubuntu-16.04 to ubuntu-latest

Bump Hardfloat in Preparation for Chisel 3.5

fix build errors with mill

* see https://github.com/com-lihaoyi/mill/discussions/1396#discussioncomment-969512
  for more information

* PTW: timing L2TLB valid select write way

* Reg:=Wire instead of Wire:=Reg

Add instructions for signing the Chips Alliance CLA

* convert TestHarness to chisel3, work around compatibility mode naming issue.

* explicit tieoff in axi4 bundle.

* use DontCare.

* DCache does not block Acquire/ProbeAck by outstanding Release

* include more bits in the block_probe_for_pending_release_ack address comparison to eliminate most false positives

* tl_out_a block acquire for pending release_ack: include address comparison to eliminate most false positives

* tl_out_a block acquire for pending release_ack: use s2_req.addr for address comparison to improve timing