Add hypervisor extension (#2841)

This PR implements v0.6.2 of the RISC-V Hypervisor Extension.

The implementation was inspired by José Martins' and colleagues' work
described in [1]. Much of the microarchitecture and essentially all of
the code is new, but their implementation served as our baseline.
We thank them for trailblazing hypervisor support in rocket-chip.

Note that this PR only includes the mechanisms to virtualize the hart
itself. Virtualized interrupt controllers, IOMMUs, etc. are future work.
Lots of future work.

Note also that some features are (legally) not implemented. Currently,
misa.H is not writable, something we may or may not choose to fix.
The mtinst and htinst CSRs are hardwired to 0, placing
additional onus on hypervisor software to use the HLVX instruction.

[1] "A First Look at RISC-V Virtualization from an Embedded Systems Perspective", https://arxiv.org/abs/2103.14951



Co-authored-by: John Ingalls <john.ingalls@sifive.com>