(cherry picked from commit 399ef9e0)

# Conflicts:
#	README.md

riscv-tests.suite[] wont compile

(cherry picked from commit d86c011d)

L1TLB: VS-mode SFENCE misses tera/giga-page entries fragmented superpages (backport #3297)

(cherry picked from commit 8b52a6f6)

Nix 2.14 released with incompatibilities with cachix/install-nix-action.
This PR pins nix to 2.13.3 to avoid CI fails
See: https://github.com/cachix/install-nix-action/issues/161

(cherry picked from commit 84533ae0)

Relax dependencies on HasPeripheryDebug (backport #3279)

(cherry picked from commit 0e4af6df)

(cherry picked from commit a2682ca3)

(cherry picked from commit 34d73098)

This was introduced by "(185cac83) Add hypervisor extension (#2841)"

This is a dead code, as no circuit is producing and consuming
this bit.

This was discovered when migrating Core.scala to chisel3, where
strict checking was applied for IO and firrtl found this is
not connected.

In the context of hypervisor extension, V bit, or _virtualization
mode_, indicates whether the hart is currently executing in a
guest.

For TLBReq, the V bit is needed as it affects the PTW thus TLB
behavior on whether to do _Two-Stage Address Translation_.

However, the bit is not needed for TLBException. The exceptions
(pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point
to add V bit for gf (guest page fault).

The io.resp.gf added below in the original patch also does
not connect io.resp.gf.v. If this V bit should be added
for this specific exception, it should be connected.

I assume this was added accidentally, as the original
"extends CoreBundle()(p)" modification seems irrelevant.

This removes a redundant port
As rnum is encoded in rs2 as imm now,
we can get it just from rs2

It is not rs2, it is imm
Related to https://github.com/chipsalliance/rocket-chip/issues/3255

scala.reflect.internal.Types: constructor RecordMap in class RecordMap cannot be accessed in package util from package util in package rocketchip

Cherry-picked https://github.com/chipsalliance/chisel3/commit/7372c9e2eed082d35abbe55f856d03fda68dc0be
Should use BarrelShifter from chisel3.std, but it is not published,
see https://github.com/chipsalliance/chisel3/pull/2997

util: fix errors during FIRRTL pass

Assorted fixes for scala 2.13/chisel 3.5.5