This change conditionally updates what verilog is needed
to build a simulator based on *.rom.conf
In order to get this working we need to re-excute make after
chisel has been run, this is done whenever an included makefile
is changed. Before now we have only needed this re-execution for
the list of tests to run but we now need it to know how to build
the simulator.
We also exclude this inclusion for dryruns.

The bootrom code is now parameterized to be able to
build bootrom or maskrom style images.
You can mark periphery mask rom's as bootable and
the bootrom is now optional to allow the maskrom to
take its place.
Also a small verilator fix to the vlsi_rom_gen script

This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.

Fix acquire before release

Add a +max-core-cycles PlusArg

If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.

oops...

Don't trigger ECC writebacks when a release is in flight

This is an acquire-before-release regression.

If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.

These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.

Fix IBuf bug

Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)

memgen: also randomize ren and rand register

Bump riscv-tools to bump riscv-tests for mi-csr test fix.

Bus blocker lock

Don't merge stores that manifest WAW hazards

Improve and use vlsi_mem_gen for verilator flow

The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.

tilelink: PMP controlled BusBlocker prevents bus accesses

Perform tag error detectoin/correction in same cycle as RAM

Don't report to the DTIM that data is cacheable

Otherwise, it will attempt to perform AMOs where they're unsupported!