This improves WCET bounds.

Move a bunch more things into util package

A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util

Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.

These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.

[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356)

The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.

The NastiConverterTest, PCIeMockupTest, and DirectGroundtest
configurations have been broken by recent changes.

The NastiConverterTest has been superseded by a unit test and the
other two were only created for an attempt at FPGA debugging.
They weren't actually very useful for that purpose, so might as well get
rid of them.

These were made for a previous Hurricane tapeout, but we are now doing
all of the memory routing in TileLink, so they are no longer needed.

crossing: Remove reset from the logic in Register Crossing 

The mask of a Get should also be converted.

This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.

crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations

 * Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams

This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.

We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.

* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}

* tilelink2: use addr_lo instead of relying on truncation

Truncation can mess up if the width should be 0, but IS 1.