update torture support scripts to work better
with multi-lane designs

* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires

Bump riscv-tools to get new riscv-isa-sim

Assorted changes based on ISP use cases

Always safe because of the requirement on coreplex/RocketTiles.scala:126

ISP fixes

Track commit 274d908d

Track commit 985d9750

Track the change made in 59947149

Improve integer mul/div

* refactor ICache to be reusable by other frontends

specifically one that would like to change the fetch width and number of
bytes in an instruction

specifically one that would like to change the fetch width and number of
bytes in an instruction

- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.

vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters

Check for rvc before declaring illegal instruction after an ebreak.

travis: attempt to make 2 build stages for cache

Timeouts due to inactivity again :-/

First stage builds riscv-tools, next stage builds verilator

This should make an optimal circuit for a wider class of ranges.

Bump riscv-tools to pick up FESVR which allows starting all harts

Inter-System-Port