Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter

async_reset_reg: Squash X's the same as for synchronous reg

Respect ISA requirements on interrupt priority order

chooseInterrupts already sorts M interrupts above S interrupts.

https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3

Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.

jtag_vpi: Use Parameterized Black Box 

This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.

Fix acquire before release

Add a +max-core-cycles PlusArg

If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.

oops...

Don't trigger ECC writebacks when a release is in flight

This is an acquire-before-release regression.

If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.

These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.

Fix IBuf bug

Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)

memgen: also randomize ren and rand register

Bump riscv-tools to bump riscv-tests for mi-csr test fix.

Bus blocker lock