I broke this in 1d46b6a6

I will investigate why regression testing didn't catch this.

Several QoR and minor generator functionality improvements for Rocket-related utilities

Move the ECC encoders to the input side of the arbiter, rather than the
output side.  This allows encoding to proceed in parallel with computing
the arbiter control signals, which are on the critical path.

Leverage the popularity of contiguous virtual mappings to reduce the
number of CAM ports for the same TLB reach.

This control change allows the write-data computation to proceed before
the write-enable is actually known.

Even though there's not really a way mux when nWays = 1, there's still
a mux between the SRAM and TL.D for uncached load responses.  It's
sometimes profitable to pipeline that.

The datapath for refilling a D$ does not belong in a DTIM.

Also, simplify TL-D opcode decoding, pruning some bits.

Leverage the fact that nacks are unlikely to cut these paths:

dmem.s2_nack -> dmem.req.valid
dmem.resp.valid -> tl.d.bits.data

Debug: Move DMI-specific code to a seperate file

Model AsyncResetReg's init reset behavior as level-sensitive

A one-character PR!

Fix AsyncResetReg

Using SFENCE with rs1 != x0 relies on reusing the TLB hit path, but it's
not possible to hit when VM is disabled, so the logic did the wrong thing.
The simple fix is to flush the whole TLB when using SFENCE when VM is
disabled.  This shouldn't be an important performance case, because SFENCE
is nearly only used when VM is enabled (for obvious reasons).

This makes it possible to output several DTS snippets we can cat together.

This was erroneously masking id_csr_en by id_ctrl.fp; these control
signals are mutually exclusive.  Fix that, and also optimize the stall
logic to avoid stalling on unrelated CSR accesses.