Use Scala212-compatible versions of chisel3 and firrtl; bump compiler to 2.11.11; bump sbt to 0.13.16

Remove global fields PAddrBits and ResetVectorBits

Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.

Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.

Add Parameters to diplomatic edges

This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.

Whether or not a Monitor should be placed is decided by diplomacy.

This has been good practice for ages. Enforce it.

These are faster and small don't cost much more.

Cleanup some register primitives

jtag_vpi: add some hysteresis for waiting for init_done

shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.