- Mar 13, 2020
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Wesley W. Terpstra authored
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Megan Wachs authored
* Build AsyncResetSynchronizerShiftReg from new SynchronizerPrimitive * SyncResetSychronizer: Construct out of single bit shift regs * ShiftReg: Add comment to distinguish types * Synchronizers: Refactor how the SynchronizerShiftReg are done internally * Synchronizers: no longer allow specification of reset value * Synchronizers: remove some redundant withReset * Synchronizers: update interrupt crossings to deal with the requirement that async crossings are truly async and marked with SynchronizerPrimitiveShiftReg * AsyncQueue: only use synchronizers of a fixed depth * Synchronizers: Add initial values back to the API * Debug Synchronizers: revert change now that initialization is back in the API * synchronizers: fix typo in parameter ordering, restore some additional API * Crossing: deprecate instead of delete the heavily used IntSyncCrossingSink API for asynchronous interrupt crossings * Synchronizers: fix the postfixing of the primitive * Allow SynchronizerShiftReg to have a special case of 0 where we just assign out to in * Allow SyncResetSynchronizerShiftReg to have a special case of 0 where we just assign out to in * Synchronizer: don't touch the ports so that the primitive I/O is predictable even when data is constant * travis: bump to python3-pexpect since gdbserver.py was bumped to python3 * Revert "travis: bump to python3-pexpect since gdbserver.py was bumped to python3" This reverts commit 74ae7576cf643259de3227eacb0ac4f644361be2. * Synchronizer: workaround for a chisel bug to keep I/O names stable * Revert "Synchronizer: don't touch the ports so that the primitive I/O is predictable even when data is constant" This reverts commit a9e83e42222e9ba5e616a408a09123f1fa10a39f. Co-authored-by:Ryan Macdonald <rmac@sifive.com>
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- Mar 12, 2020
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Wesley W. Terpstra authored
BundleMap: improved API for user bits
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Megan Wachs authored
Multiplier: Make MultiplierIO clone-able
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Bradley Morrell authored
Support for versioning in diplomacy (old userbits)
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Ryan Macdonald authored
BaseSubsystem: Rename attach method and traits
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- Mar 11, 2020
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Megan Wachs authored
Trying to resolve warning: [deprecated] class freechips.rocketchip.rocket.MultiplierIO (1 calls): Unable to automatically infer cloneType on class freechips.rocketchip.rocket.MultiplierIO: constructor has parameters (dataBits, tagBits) that are not both immutable and accessible. Either make all parameters immutable and accessible (vals) so cloneType can be inferred, or define a custom cloneType method. [warn] There were 1 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues. [
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
- Field unification can be customized and defaults to equality required - Bulk assignment of BundleMaps now uses defaults for missing fields - You must now define both a Field and Key class
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Ryan Macdonald authored
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Henry Cook authored
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Ryan Macdonald authored
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Deborah Soung authored
* Revert "updating README examples with Make changes (#2322)" This reverts commit 875dcd3e. * Revert "fixing aspect generation (#2309)" This reverts commit bbeb2578. * Revert "separate generator behavior into phases (#2274)" This reverts commit 9d997506.
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- Mar 10, 2020
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Bradley Morrell authored
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Bradley Morrell authored
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Bradley Morrell authored
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Bradley Morrell authored
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Bradley Morrell authored
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- Mar 07, 2020
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Deborah Soung authored
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Bradley Morrell authored
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Bradley Morrell authored
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Bradley Morrell authored
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Andrew Waterman authored
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Deborah Soung authored
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- Mar 06, 2020
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Bradley Morrell authored
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- Mar 05, 2020
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Bradley Morrell authored
Grabbed changes from commit: e81dd8b2
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Henry Cook authored
prci: allow configurable ClockGroupDriver drive function
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- Mar 04, 2020
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Henry Cook authored
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Ernie Edgar authored
Qualify load and store watchpoints by instruction type
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Ernie Edgar authored
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Suraj Narayan Vellengar authored
* assertion for speculative fetch chicken bit * removed the assertion as it may fail due to race condtion
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- Mar 03, 2020
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Megan Wachs authored
APBToTL: Qualify address alignment assertion
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- Mar 02, 2020
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Megan Wachs authored
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- Feb 29, 2020
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Deborah Soung authored
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Henry Cook authored
in particular, handle the common failure scenario where an L1 DCache is added to a design with no cacheable memory region.
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- Feb 28, 2020
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Bradley Morrell authored
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