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chipsalliance
rocket-chip
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om-corecomplex-add-rtlmodule
038f9064
·
corecomplex-add-rtlmodule
·
Dec 17, 2018
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base-tile-retire-width
81a26f93
·
BaseTile: Expose retirement width
·
Dec 17, 2018
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om-rtlmodule-update
8e7a7074
·
adding default None's to the OMRTL schemas
·
Dec 17, 2018
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trace-bundle-bridge
ba59b3ab
·
BundleBridge: Fix API bug
·
Dec 14, 2018
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nomi6
c954e847
·
merge
·
Dec 07, 2018
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nomi8
a4058033
·
Merge branch 'master' of github.com:freechipsproject/rocket-chip
·
Nov 30, 2018
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event_covers
c9c37120
·
Fix event covers to eliminate dead covers
·
Nov 27, 2018
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bb-comment
fdb6ed07
·
Update BundleBridge.scala
·
Nov 19, 2018
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remove-splitter
65e41ff7
·
tilelink: remove NodeNumberer and Splitter
·
Nov 09, 2018
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bus-views
2b801c32
·
subsystem: offer view from all bus wrappers
·
Oct 31, 2018
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nomi1
ec02c696
·
updating
·
Oct 28, 2018
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pbus-totile-ww
0cb98f67
·
Merge remote-tracking branch 'origin/master' into pbus-totile-ww
·
Oct 23, 2018
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RVFI
3ce023df
·
Add misa register monitor and priv mode
·
Oct 18, 2018
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bundle-bridge-broadcast
cc58f2ad
·
tmp
·
Oct 08, 2018
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better-hints-2
bc9d631d
·
subsystem: can still put error on sbus
·
Oct 06, 2018
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register-router-redux
4d3ba3dc
·
registerrouter: remove unused type parameter
·
Sep 27, 2018
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beu-fix-dontdeleteme
00d57ffd
·
bump riscv-tools for debug workaround
·
Aug 25, 2018
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bundle-bridge-splice
f01b175c
·
bundlebridge: first cut of splice
·
Aug 21, 2018
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dcachedip
79330707
·
changed PTW's interface to take in a function that returns the number of ports...
·
Aug 17, 2018
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rocc_dip
88714d37
·
fixed whitespace issues, changed package from tile.fpucp to rocket.fpucp per...
·
Aug 16, 2018
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