Custom CSR hooks can now tell exactly which csr instruction were used

Replaced with a slightly less broken version

tdata3 is optional.  We should have a better way of supporting
different configurations, but it's safe to drop for now.

In order of severity
- claim access didn't work (word vs byte index confusion)
- 0-based/1-based confusion cased pending to not match actual irq
- reading claim must clear the pending interrupt
- disabled sources still triggered
- context assignement wasn't respected
- contexts weren't being distinguished
- VIRTIO_IRQ assignment clashing with hardwired devices

Note, this is the minimal change I could make to get it fixed.  It
still doesn't handle priorities and the code is in desperate need of
restructuring (and name fixing).  The PLIC in QEMU (sifive_plic.c) is
very clean and should be use as gold standard.

To make this slightly easier to build, don't depend of standard
headers as they aren't present by default for some cross tool chains.

Signed-off-by: damageboy <125730+damageboy@users.noreply.github.com>

Signed-off-by: damageboy <125730+damageboy@users.noreply.github.com>

Use intrinsic clz for bitcounting. While clz is not available, use
branchless implementation instead.

Commit d8689621 slipped in an presumedly unintential enable of dumping
the DTB

If

  c.addr + c.addr.size == addr

then regions where incorrectly considered partially overlapping and
likewise for

  addr + addr.size == c.addr

NB: There's a faster way to check for partial overlap, but we'll keep
the change minimal here.

- pass dhrystone with cosim+goldmem
- pass all the tests with inorder goldmem
- fix goldmem AMO, and create a regression to cover all the options
- add manual regression ./run/regression.sh

Added a detailed tutorial on how to integrate Dromajo for cosimulation.
The tutorial describes integration into Ariane core but intention was to give
the reader an idea how to apply steps for their own core.

Rather that rewriting each prior commit, fix it all here.

Factor out the creation of the bootram
+ cleaned much boiler plate in the config parser.

RISCVEMU originally included a short, but hard-coded bootrom.  That
evolved organically to an ever more complicated bootrom generation,
which was finally supplemented by the now perfered option of loading a
custom bootrom.

This change include a small example rom, and reorganizes the bootrom
handling code slightly.

+ Tweak debugging output