The RISC-V Privileged Architectures V1.11-draft says:

  "The FS[1:0] read/write field and the XS[1:0] read-only field are
   used to reduce the cost of context save and restore by setting and
   tracking the current state of the floating-point unit and any other
   user-mode extensions respectively. The FS field encodes the status
   of the floating-point unit, including the CSR fcsr and
   floating-point data registers f0–f31.."

As fcvt.{w,wu,l,lu}.[sdq] and FP compares _could_ potentially set the
NV (Invalid Op) exception bit in FCSR, we must mark the state as dirty
in FS.  I'm assuming it's ok to be conservative here and mark it dirty
even if no new bit was actually set.  It's clearly not ok, to _not_
mark it dirty if one was set.

There is still one FP instruction that doesn't set FS (fclass), though
it would probably be acceptible to set the FS bit there as well.

We accidentally threw exceptions previously

Turn off the logging by default.

Unless we are tracing or cosimulating, we should run for a long as
possible inside riscv_cpu_interp64().  This change speeds up normal
execution by a large amount.

Don't clear that bit as we have no path to turn it on again.  This
change enables output with interrupts enables (used to hang).  It's
still lacking periodic polling which is required for input to work.

Now by default Ctrl-C will not stop emulation but is sent to the guest.
To enable breaking out C-b is used as a prefix key:

  C-b h   print help
  C-b x   exit emulator
  C-b C-b send C-b

- Quell GCC warnings (by casting ignored return values)
- Fix `--dump_memories`; it never took an argument
- No Tabs in Source Code!
- Code clean up

The cmake crate requires this and it doesn't affect the current build

mmio range cfg/arg removed: any address access that isn't mem-mapped as virtIO or RAM is now propagated from DUT in cosim

Custom CSR hooks can now tell exactly which csr instruction were used

Replaced with a slightly less broken version

tdata3 is optional.  We should have a better way of supporting
different configurations, but it's safe to drop for now.

In order of severity
- claim access didn't work (word vs byte index confusion)
- 0-based/1-based confusion cased pending to not match actual irq
- reading claim must clear the pending interrupt
- disabled sources still triggered
- context assignement wasn't respected
- contexts weren't being distinguished
- VIRTIO_IRQ assignment clashing with hardwired devices

Note, this is the minimal change I could make to get it fixed.  It
still doesn't handle priorities and the code is in desperate need of
restructuring (and name fixing).  The PLIC in QEMU (sifive_plic.c) is
very clean and should be use as gold standard.

To make this slightly easier to build, don't depend of standard
headers as they aren't present by default for some cross tool chains.

Signed-off-by: damageboy <125730+damageboy@users.noreply.github.com>