sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-01-14	Reorganize directory structure.	Prashanth Mundkur	1	-131/+0
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur	1	-0/+3
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur	1	-0/+3
2018-07-10	Add an option to specify the dtc to use for the riscv platform.	Prashanth Mundkur	1	-1/+4
2018-07-09	Log some timing info at the end of riscv execution.	Prashanth Mundkur	1	-5/+20
2018-06-25	Add a riscv platform parameter to control trapping to M-mode on misaligned ac...	Prashanth Mundkur	1	-1/+4
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur	1	-3/+7
2018-06-22	Add cli options to riscv simulator to dump platform device-tree info.	Prashanth Mundkur	1	-1/+13
2018-06-22	More trace log tweaks.	Prashanth Mundkur	1	-2/+2
2018-06-11	Put the riscv model's output on stderr, leaving stdout for the platform termi...	Prashanth Mundkur	1	-1/+1
2018-06-04	Add the htif exit command, a top-level function to initialize the riscv platf...	Prashanth Mundkur	1	-1/+2
2018-05-21	Start platform execution at the reset-vector in the rom.	Prashanth Mundkur	1	-17/+13
2018-05-21	Add in the platform files and update the ocaml build. Disable the isabelle b...	Prashanth Mundkur	1	-0/+91