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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-11-21 14:02:18 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-11-21 14:19:21 -0800 |
| commit | af539244ab7ae465e6081ecbe5ee1cdf797b69ab (patch) | |
| tree | 4df161e4931eb78248f53a665f7817e168233c0e /platform_main.ml | |
| parent | 78499cf7a2b3a76ca5de729ea093ccf49f894c16 (diff) | |
| download | sail-riscv-af539244ab7ae465e6081ecbe5ee1cdf797b69ab.zip sail-riscv-af539244ab7ae465e6081ecbe5ee1cdf797b69ab.tar.gz sail-riscv-af539244ab7ae465e6081ecbe5ee1cdf797b69ab.tar.bz2 | |
RISC-V: allow platform ram size to be configurable.
Diffstat (limited to 'platform_main.ml')
| -rw-r--r-- | platform_main.ml | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/platform_main.ml b/platform_main.ml index b33247f..1c9ba20 100644 --- a/platform_main.ml +++ b/platform_main.ml @@ -76,6 +76,9 @@ let options = Arg.align ([("-dump-dts", ("-mtval-has-illegal-inst-bits", Arg.Set P.config_mtval_has_illegal_inst_bits, " mtval stores instruction bits on an illegal instruction exception"); + ("-ram-size", + Arg.Int PI.set_dram_size, + " size of physical ram memory to use (in MB)"); ("-with-dtc", Arg.String PI.set_dtc, " full path to dtc to use") |