| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-11-21 | RISC-V: allow platform ram size to be configurable. | Prashanth Mundkur | 1 | -6/+11 |
| 2018-10-23 | RISC-V: use stderr for terminal output in OCaml backend. | Prashanth Mundkur | 1 | -1/+1 |
| 2018-07-10 | Add an option to specify the dtc to use for the riscv platform. | Prashanth Mundkur | 1 | -2/+15 |
| 2018-07-03 | Allow the riscv htif_tohost mmio port to be readable, and ack writes to that ... | Prashanth Mundkur | 1 | -1/+1 |
| 2018-06-22 | Add cli options to riscv simulator to dump platform device-tree info. | Prashanth Mundkur | 1 | -3/+8 |
| 2018-06-13 | Tracing instrumentation for C backend | Alasdair Armstrong | 1 | -1/+1 |
| 2018-06-07 | Add terminal output to riscv platform, with incomplete handling of input. | Prashanth Mundkur | 1 | -0/+11 |
| 2018-05-23 | Fix incorrect channel in dtc i/o. | Prashanth Mundkur | 1 | -1/+1 |
| 2018-05-21 | Start platform execution at the reset-vector in the rom. | Prashanth Mundkur | 1 | -1/+1 |
| 2018-05-21 | Add in the platform files and update the ocaml build. Disable the isabelle b... | Prashanth Mundkur | 1 | -0/+155 |
 |
index : sail-riscv.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |
path: root/platform_impl.ml