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Likely a cut-and-paste error, the definition for fmaxm.d uses the fmaxm.s
mnemonic, which is already used earlier in the same file.
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both should be disabled if F=0
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In some cases we were reporting the translated value instead, but the
privileged spec text requires the virtual address:
```
If mtval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then mtval will contain the faulting
virtual address.
```
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Since Sail 0.15 (released Nov 2022), effects have had no effect. They now generate a deprecation warning. This commit removes all the effect annotations from the model, thus fixing the compiler warnings.
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These are given on the previous line already. Sail does not let you change the type of a variable like Rust does. The `var` ensures this definitely refers to a local rather than global variable.
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This is already provided by Sail.
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Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
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This strips trailing whitespace and fixes line endings. I had to add the
*.dump files to the exclude list to avoid excessive changes, but
ideally these would not be part of the repository since they can just be
generated by running objdump manually.
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PR #257 was aggressively merged before all coding-style issues had
been commented on. This addresses the issues that came up (except the
drive-by whitespace cleanup that was contained in PR #257 and would
require a force-push) in review.
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This commit adds the following:
- infrastructure for Zfa (e.g., existence macro)
- support for the following instructions:
+ FLI.[HSD]
+ FMINM.[HSD] and FMAXM.[HSD]
+ FROUND.[HSD] and FROUNDNX.[HSD]
+ FMVH.X.D and FMVP.D.X
+ FLEQ.[HSD] and FLTQ.[HSD]
+ FCVTMOD.W.D
Note the following implementation details:
FMINM and FMAXM provide similar functionality to FMIN and FMAX,
differing only in their NaN-handling:
* FMIN/FMAX return a canonical NaN only if both operands are a NaN
* FMINM/FMAXM return a canonical Nan if any operand is a NaN
Consequently, the implementation is identical to FMIN/FMAX with only
the NaN-related tests changed.
FROUND instruction rounds a floating-point number in floating-point
register rs1 and writes that integer, represented as a floating-point
number to floating-point register rd while:
* Zero and infinite inputs are copied to rd unmodified.
* NaN inputs cause the invalid operation exception flag to be set.
FROUNDNX instruction is defined similarly, but also sets the inexact
exception flag if the input differs from the rounded result and is not
NaN.
FMVH.X.D instruction is available for RV32 only and moves bits 63:32
of floating-point register rs1 into integer register rd.
FMVP.D.X instruction is available for RV32 only and moves a
double-precision number from a pair of integer registers into a
floating-point register. Integer registers rs1 and rs2 supply bits
31:0 and 63:32, respectively.
FLEQ and FLTQ instructions are defined like the FLE and FLT
instructions, except that quiet NaN inputs do not cause the invalid
operation exception flag to be set.
The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D
instruction, with the following differences:
* FCVTMOD.W.D always rounds towards zero.
* Bits 31:0 are taken from the rounded, unbounded two's complement
result, then sign-extended to XLEN bits and written to integer
register rd.
* Positive infinity, negative infinity and NaN are converted to zero.
Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
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This fixes a small bug in `mcounthinhibit`. In the current code if you set `mcountinhibit=1` then it inhibits the count of that CSR write, whereas the spec says that it should only apply to future instructions:
> Any CSR write takes effect after the writing instruction has otherwise completed.
- From the priviledged spec, section 3.1.10 Hardware Performance Monitor.
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range limit are the same then no pmp match
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This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
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Only reporting the address (without data) on failures matches QEMU.
This also drops the call to rvfi_write from phys_mem_write since that
would result in (harmless) duplicate trace value updates.
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Half-precision loads/stores should not be allowed if mstatus.FS is set to
0 to match single/double-precision ones.
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This may be more readable and also matches the sail-cheri-riscv model.
For now this keeps ~ overloaded to accept bool, but in the future we may
want to consider removing it (which is what I did to find all uses
modified in this patch)
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This is useful for the sail-cheri-riscv model, where we would like to
reuse C_ILLEGAL, but can't right now since it is current defined too late.
It is needed for https://github.com/CTSRD-CHERI/sail-cheri-riscv/pull/69
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Sail tries to check for pattern match completeness and issues warnings
but this often gives false positives: see discussion at
https://github.com/rems-project/sail/issues/191 . To suppress these
we add a wildcard case that raises an internal error. There is
effectively no behaviour change as these would previously have
resulted in a match error at runtime and they should be unreachable
anyway.
At the same time we change the DOUBLE case in memory access paths to
allow for xlen > 64.
Following discussion on the PR I also changed internal_error to take a
file and line number as an argument to aid with debugging.
Fixes: https://github.com/riscv/sail-riscv/issues/194
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This can now be found in the Sail repository.
Includes an update to sail-riscv.install
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-X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)" (#220)
Reverts #219. Merged without code review and with many issues.
This reverts commit 43b81eafc660ab584e1684668995957764a5e684.
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-X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)
* added 3 command-line switches: -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond
* example commit
* fixed some type warnings/errors (between int/bool)
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Previously the decoding hook (`ext_post_decode_hook`) allowed models to
override the decoded `ast`. However, this is not sufficient if model
extension changes interpretation of fields. Additionally, the assembly
printing would always print assembly for the "baseline decode" which
resulted in incorrect trace output in the sail-cheri-riscv model.
With the new hook models can implement ext_decode()/ext_decode_compressed()
to return an `ast` and for encodings that are not adjusted fall back to
the default `encdec`/`encdec_compressed`.
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Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>
Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>
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Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>
Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>
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This option causes handle_illegal to pass instbits as the value to set
for xtval, but instbits is never set so it ends up being 0 just as if
the option was never enabled. Fix this by initialising instbits during
fetch; we could make this conditional on whether the option is enabled
but that seems unnecessary and introduces tighter coupling.
Note that this option appears to have always been broken; when it was
originally added, instbits was only written two in two cases which were
both dead code and later removed in eb176111887b.
Closes: #173
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Merged after code review. Thanks everybody for helping.
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NB: Smstateen support is missing in the model so enabling the Zfinx
extension provides an architectural covert channel via FCSR if
privileged software is not aware of Zfinx's existence.
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Ibrahim Abu Kharmeh <abukharmeh@gmail.com>
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This reverts commit c5e62ea4b3d481fcd491b22b317cc319b089f05d.
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* Adds Zfinx enable flag
* Hardwire misa.{f,d} and mstats.FS to 0
* Moving nan boxing functions to fdext_reg
* Swaps register names for floating point instructions
Adds new mapping to swap register names, and use it in all assembly clauses
* Disable Floating point loads, stores and moves
* Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points
Changes register accessed for floating point instructions and modify nan boxing functions for zfinx
* Formatting
Remove couple of misplaced whitespace, unnecessary parens
* Fix inconsistent indentation in insts_dext file
* Fix spacing in fdext_regs
* Remove redundant comparasion with true/ false
* Constistant tuples spacing and removes couple of unnecessary parens.
* Consistent functions declaration & calls spacing and removes couple of unnecessary parens.
* Consistent spacing and removes couple of unnecessary comparasion with true/false
* Make spacing consistent
* Remove checks from execution stage
* Add checks to encdec stage
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Trying to make the behavior of aesks1i easier to understand, and more
obviously correspond to the specification.
- Ensure that the aes_decode_rcon function only accepts valid values, plus
add comments.
- Re-name operands to aesks1i rcon -> rnum to be in line with the specification
- Re-structure the Sail code for clarity based on jrtc27's suggestion.
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Remove weird whitespace " );" -> ");" at end of expressions to be
consistent with the rest of the code base.
On branch scalar-crypto-tidy
Changes to be committed:
modified: model/riscv_insts_zkn.sail
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Add spaces pre/post used of "==" operator to be consistent with the rest
of the code.
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File is no longer needed, as per this discussion: https://github.com/riscv/sail-riscv/issues/119
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* Use bool for floating point comparison result
Using bits_WU (bits(32)) or bits_LU (bits(64)) makes no sense, these are
just boolean values, and having fixed-width types is a pain for
suporting RV32D (since RV32D would need to truncate, but RV128D would
need to extend). Instead represent these as an actual bool to match what
the values really are. This could be done with bits(1) but the value is
logically a boolean (like the built-in integer comparison operators) not
a bit vector of length one so we convert to bool and back for a cleaner
interface.
* Support compiling RV32F with flen == 64
The code conflated flen and xlen; deconflating them and adding suitable
assertions (rather than silently retiring as a no-op that doesn't bump
instret) ensures that it can be compiled for RV32 with flen set to 64.
Whilst here, add the extensions and truncations that would be needed for
RV128F.
Note that there are already suitable guards on the decode clauses to
ensure these instructions are illegal on RV32.
* Support compiling RV32D
This copies various bits of XLEN generality from the F code.
* Support RV32D loads/stores
* Correctly initialise misa.D based on flen not xlen
* Makefile: Enable D extension for RV32
This now works so can be enabled.
* test: Enable RV32D tests
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Merged scalar-crypto pull request #99 of 1.0.0-rc2 spec work from Ben Marshall. See https://github.com/riscv/sail-riscv/pull/99.
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Fix crash when fcsr.frm is invalid
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This is required for implementing memory version support for CHERI.
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It's possible that we might want to do page table walks at Privilege levels
other than the default value (e.g., under the explicit direction of the
instruction stream). Split translateAddr into a thin wrapper of the same name
and a new translateAddr_priv that takes the Privilege as an argument.
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