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| author | Bill McSpadden <bill@riscv.org> | 2023-02-13 19:50:46 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-13 19:50:46 -0600 |
| commit | 43b81eafc660ab584e1684668995957764a5e684 (patch) | |
| tree | 97aebab0afe29b8c0b1f8d9d4dc6a1c2c1f9afbe /model | |
| parent | 9547a30bf84572c458476591b569a95f5232c1c7 (diff) | |
| download | sail-riscv-43b81eafc660ab584e1684668995957764a5e684.zip sail-riscv-43b81eafc660ab584e1684668995957764a5e684.tar.gz sail-riscv-43b81eafc660ab584e1684668995957764a5e684.tar.bz2 | |
added 3 new command line switches (plus functionality): -X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)
* added 3 command-line switches: -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond
* example commit
* fixed some type warnings/errors (between int/bool)
Diffstat (limited to 'model')
| -rw-r--r-- | model/riscv_platform.sail | 17 | ||||
| -rw-r--r-- | model/riscv_sys_regs.sail | 6 |
2 files changed, 23 insertions, 0 deletions
diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail index ea27f48..6b8ce3d 100644 --- a/model/riscv_platform.sail +++ b/model/riscv_platform.sail @@ -116,6 +116,23 @@ val plat_mtval_has_illegal_inst_bits = {ocaml: "Platform.mtval_has_illegal_inst_ c: "plat_mtval_has_illegal_inst_bits", lem: "plat_mtval_has_illegal_inst_bits"} : unit -> bool +/* whether the Smepmp extension is supported */ +val plat_enable_smepmp = { + c: "plat_enable_smepmp" + } : unit -> bool + +/* whether the Smepmp extension is supported */ +val plat_enable_zicond = { + c: "plat_enable_zicond" + } : unit -> bool + +/* whether the model supports extensions/CSRs/functionality that is considered "experimental" */ +/* this is meant to support testing of extensions that are in development but have not */ +/* been ratified. */ +val plat_enable_experimental_extensions = { + c: "plat_enable_expermimental_extensions" + } : unit -> bool + /* ROM holding reset vector and device-tree DTB */ val plat_rom_base = {ocaml: "Platform.rom_base", interpreter: "Platform.rom_base", c: "plat_rom_base", lem: "plat_rom_base"} : unit -> xlenbits val plat_rom_size = {ocaml: "Platform.rom_size", interpreter: "Platform.rom_size", c: "plat_rom_size", lem: "plat_rom_size"} : unit -> xlenbits diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 9cc5034..c2952a5 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -148,6 +148,12 @@ val sys_enable_fdext = {c: "sys_enable_fdext", ocaml: "Platform.enable_fdext", _ val sys_enable_zfinx = {c: "sys_enable_zfinx", ocaml: "Platform.enable_zfinx", _: "sys_enable_zfinx"} : unit -> bool /* whether the N extension was enabled at boot */ val sys_enable_next = {c: "sys_enable_next", ocaml: "Platform.enable_next", _: "sys_enable_next"} : unit -> bool +/* whether the Smepmp extension was enabled at boot */ +val sys_enable_experimental_extensions = {c: "sys_enable_experimental_extensions"} : unit -> bool +/* whether the Smepmp extension was enabled at boot */ +val sys_enable_smepmp = {c: "sys_enable_smepmp"} : unit -> bool +/* whether the Zicond extension was enabled at boot */ +val sys_enable_zicond = {c: "sys_enable_zicond"} : unit -> bool /* This function allows an extension to veto a write to Misa if it would violate an alignment restriction on |