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author | Alex Richardson <alexrichardson@google.com> | 2023-09-08 06:36:48 -0700 |
---|---|---|
committer | Bill McSpadden <bill@riscv.org> | 2023-09-20 10:09:42 -0500 |
commit | c60091a6e545534f666448e7ea7514d3b876da93 (patch) | |
tree | fd7582785d5b67b59af0106601dadab2e257c988 /model | |
parent | 4c77f62622c199f14e0bd6cdc6a6c427fe31b09e (diff) | |
download | sail-riscv-c60091a6e545534f666448e7ea7514d3b876da93.zip sail-riscv-c60091a6e545534f666448e7ea7514d3b876da93.tar.gz sail-riscv-c60091a6e545534f666448e7ea7514d3b876da93.tar.bz2 |
Report the faulting virtual address in tval
In some cases we were reporting the translated value instead, but the
privileged spec text requires the virtual address:
```
If mtval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then mtval will contain the faulting
virtual address.
```
Diffstat (limited to 'model')
-rw-r--r-- | model/riscv_insts_aext.sail | 10 | ||||
-rw-r--r-- | model/riscv_insts_fext.sail | 2 |
2 files changed, 6 insertions, 6 deletions
diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail index 6915f28..ff7dc74 100644 --- a/model/riscv_insts_aext.sail +++ b/model/riscv_insts_aext.sail @@ -220,7 +220,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") }; match (eares) { - MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, MemValue(_) => { rs2_val = X(rs2); let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) { @@ -233,7 +233,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { match (res) { MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS }, MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS }, - MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL } + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } } } } @@ -303,7 +303,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = { DOUBLE => X(rs2) }; match (eares) { - MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, MemValue(_) => { let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), @@ -313,7 +313,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = { _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") }; match (mval) { - MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, MemValue(loaded) => { let result : xlenbits = match op { @@ -347,7 +347,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = { match (wval) { MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL } + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } } } } diff --git a/model/riscv_insts_fext.sail b/model/riscv_insts_fext.sail index 67f34a7..0f34c93 100644 --- a/model/riscv_insts_fext.sail +++ b/model/riscv_insts_fext.sail @@ -458,7 +458,7 @@ function clause execute (STORE_FP(imm, rs2, rs1, width)) = { DOUBLE => mem_write_ea(addr, 8, aq, rl, false) }; match (eares) { - MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, MemValue(_) => { let rs2_val = F(rs2); match (width) { |