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path: root/model/riscv_vmem.sail
AgeCommit message (Expand)AuthorFilesLines
2024-04-01Unify VM code Rishiyur S. Nikhil1-0/+452
2019-02-13Add Sv32 and Sv48 by essentially copying Sv39.Prashanth Mundkur1-59/+0
2019-02-13Pull out the Sv39 and its TLB into separate files.Prashanth Mundkur1-140/+8
2019-02-13Make more address translation types reusable.Prashanth Mundkur1-20/+15
2019-02-13Attempt to reuse types for Sv39 and Sv48 to the extent possible for simplicit...Prashanth Mundkur1-15/+15
2019-02-12Start extracting bits of vmem that should be common to RV32, and add some def...Prashanth Mundkur1-221/+11
2019-02-11Fix xlen variable name.Prashanth Mundkur1-3/+3
2019-02-11Handle SXL/UXL not being present in mstatus in RV32 by using explicit getters...Prashanth Mundkur1-1/+1
2019-02-11More refactoring for RV32Prashanth Mundkur1-3/+3
2019-02-11Parameterize CSR fields for xlen, and fix definitions for CSRs which are alwa...Prashanth Mundkur1-1/+1
2019-02-08Adapt to changes in Sail's Lem shallow embeddingThomas Bauereiss1-2/+2
2019-01-14Reorganize directory structure.Prashanth Mundkur1-0/+406