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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 11:43:01 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 11:43:01 -0800 |
| commit | 51403b862956f13a7a4fbbdd3adb72ee3518db12 (patch) | |
| tree | 264af7b86ef15002724786ba032f70ac76b6d5e8 /model/riscv_vmem.sail | |
| parent | 060c560a7d3fca3155b9b528cf1f6dfcaba22c89 (diff) | |
| download | sail-riscv-51403b862956f13a7a4fbbdd3adb72ee3518db12.zip sail-riscv-51403b862956f13a7a4fbbdd3adb72ee3518db12.tar.gz sail-riscv-51403b862956f13a7a4fbbdd3adb72ee3518db12.tar.bz2 | |
Parameterize CSR fields for xlen, and fix definitions for CSRs which are always 64-bit for RV32/RV64.
Diffstat (limited to 'model/riscv_vmem.sail')
| -rw-r--r-- | model/riscv_vmem.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_vmem.sail b/model/riscv_vmem.sail index ef56108..5c404ba 100644 --- a/model/riscv_vmem.sail +++ b/model/riscv_vmem.sail @@ -99,7 +99,7 @@ let PTE39_SIZE = 8 type vaddr39 = bits(39) type paddr39 = bits(56) -type pte39 = xlenbits +type pte39 = bits(64) bitfield SV39_Vaddr : vaddr39 = { VPNi : 38 .. 12, |