sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2024-04-14	Fix compiler warnings in vext	Ved Shanbhogue	1	-2/+2

2024-02-08	Shorten copyright notice at the top of each file	Tim Hutt	1	-37/+7
	This script was used to do the modification: ``` from pathlib import Path import re RE_LINE = r"/\={50,150}\/\n" RE_MIDDLE = r"/\.\/\n" NEW_TEXT = """/=======================================================================================/ / This Sail RISC-V architecture model, comprising all files and / / directories except where otherwise noted is subject the BSD / / two-clause license in the LICENSE file. / / / / SPDX-License-Identifier: BSD-2-Clause / /=======================================================================================/ """ REPLACEMENT = re.compile(rf"^{RE_LINE}(?:{RE_MIDDLE}){{10,100}}{RE_LINE}") def main(): for file in Path("model").glob("/.sail"): text = file.read_text(encoding="utf-8") text = REPLACEMENT.sub(NEW_TEXT, text, 1) file.write_text(text, encoding="utf-8") if __name__ == "__main__": main() ```
2023-12-06	Remove effect annotations from vector extension	Alasdair	1	-2/+2

2023-10-17	RISC-V Vector Extension Support	Xinlai Wan	1	-0/+83
	This PR adds the following: General Framework and Configurations: * Introduced the V extension's general framework and configuration setting instructions. * Updated model/riscv_insts_vext_vset.sail and effect matching functions in riscv_vlen.sail. * Addressed code formatting issues and made revisions post the Nov 22 meeting. * Co-authored by Nicolas Brunie and Jessica Clarke. Vector Load/Store Instructions: * Integrated vector load and store instructions. * Enhanced the implementation of SEW, LMUL, VLEN and removed real numbers from the code. * Updated vstart settings and removed unnecessary assert statements. * Rectified bugs in vleff instructions and overhauled coding styles. * Incorporated guards for vector encdec clauses and optimized memory access post vector load/store failures. Vector Integer/Fixed-Point Instructions: * Added vector integer/fixed-point arithmetic and mask instructions. * Improved vector EEW and EMUL checking functions and introduced illegal instruction check functions. * Fine-tuned code formatting for vector instruction checks. Vector Floating-Point Instructions: * Rolled out vector floating-point instructions and updated their conversion counterparts. * Refreshed copyright headers specific to the vector extension code. Vector Reduction and Mask Instructions: * Integrated vector mask and reduction instructions. * Addressed register overlap checks for vector mask instructions. Miscellaneous Enhancements and Fixes: * Updated vector CSR vtype.vill settings and judgements. * Systematized patterns for vector illegal instruction checks. * Rectified issues in vector load/store and reduction operations. * Purged redundant elements from the V extension code and vector floating-point functions. * Cleaned up softfloat makefiles and renamed EXTZ and EXTS within the V extension code. * Addressed a clang-format check issue and NaN boxing anomalies. Provided annotations for pending RVV configurations. * Initialized default VLEN value and set vlenb CSR. * Set constraints for vector variable initialization and added mstatus.VS settings specific to the vector extension.