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authorVed Shanbhogue <ved@rivosinc.com>2024-02-25 11:12:34 -0600
committerBill McSpadden <bill@riscv.org>2024-04-14 20:41:06 -0500
commitf1c043d76b0f5030ced7eaaea34420d3a916fd91 (patch)
tree8cd2f8a0bcdcc344ca61b58feb15d9f9463cd2b6 /model/riscv_vlen.sail
parente187e0220352e731dc15dbc7375adb3dccac8138 (diff)
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Fix compiler warnings in vext
Diffstat (limited to 'model/riscv_vlen.sail')
-rw-r--r--model/riscv_vlen.sail4
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_vlen.sail b/model/riscv_vlen.sail
index 3a2e0ac..5e45290 100644
--- a/model/riscv_vlen.sail
+++ b/model/riscv_vlen.sail
@@ -8,7 +8,7 @@
register elen : bits(1)
-val get_elen_pow : unit -> {|5, 6|}
+val get_elen_pow : unit -> {5, 6}
function get_elen_pow() = match elen {
0b0 => 5,
@@ -21,7 +21,7 @@ function get_elen_pow() = match elen {
register vlen : bits(4)
-val get_vlen_pow : unit -> {|5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16|}
+val get_vlen_pow : unit -> {5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
function get_vlen_pow() = match vlen {
0b0000 => 5,