diff options
| author | Tim Hutt <timothy.hutt@codasip.com> | 2023-12-12 08:39:21 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-02-08 19:11:14 -0600 |
| commit | 2eb3e3d265b863d41903d41ac8aa947da04c1a83 (patch) | |
| tree | 685aa9f47629ffb24a2d0200a769954836f7a6b8 /model/riscv_vlen.sail | |
| parent | 4de2bff12d967d91dd064e4a49e25ca4785f25e3 (diff) | |
| download | sail-riscv-2eb3e3d265b863d41903d41ac8aa947da04c1a83.zip sail-riscv-2eb3e3d265b863d41903d41ac8aa947da04c1a83.tar.gz sail-riscv-2eb3e3d265b863d41903d41ac8aa947da04c1a83.tar.bz2 | |
Shorten copyright notice at the top of each file
This script was used to do the modification:
```
from pathlib import Path
import re
RE_LINE = r"/\*={50,150}\*/\n"
RE_MIDDLE = r"/\*.*\*/\n"
NEW_TEXT = """/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/
"""
REPLACEMENT = re.compile(rf"^{RE_LINE}(?:{RE_MIDDLE}){{10,100}}{RE_LINE}")
def main():
for file in Path("model").glob("**/*.sail"):
text = file.read_text(encoding="utf-8")
text = REPLACEMENT.sub(NEW_TEXT, text, 1)
file.write_text(text, encoding="utf-8")
if __name__ == "__main__":
main()
```
Diffstat (limited to 'model/riscv_vlen.sail')
| -rw-r--r-- | model/riscv_vlen.sail | 44 |
1 files changed, 7 insertions, 37 deletions
diff --git a/model/riscv_vlen.sail b/model/riscv_vlen.sail index cd631ba..3a2e0ac 100644 --- a/model/riscv_vlen.sail +++ b/model/riscv_vlen.sail @@ -1,40 +1,10 @@ -/*=================================================================================*/ -/* Copyright (c) 2021-2023 */ -/* Authors from RIOS Lab, Tsinghua University: */ -/* Xinlai Wan <xinlai.w@rioslab.org> */ -/* Xi Wang <xi.w@rioslab.org> */ -/* Yifei Zhu <yifei.z@rioslab.org> */ -/* Shenwei Hu <shenwei.h@rioslab.org> */ -/* Kalvin Vu */ -/* Other contributors: */ -/* Jessica Clarke <jrtc27@jrtc27.com> */ -/* Victor Moya <victor.moya@semidynamics.com> */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*=================================================================================*/ +/*=======================================================================================*/ +/* This Sail RISC-V architecture model, comprising all files and */ +/* directories except where otherwise noted is subject the BSD */ +/* two-clause license in the LICENSE file. */ +/* */ +/* SPDX-License-Identifier: BSD-2-Clause */ +/*=======================================================================================*/ register elen : bits(1) |