aboutsummaryrefslogtreecommitdiff
path: root/model/riscv_sys_regs.sail
AgeCommit message (Expand)AuthorFilesLines
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur1-1/+4
2019-03-29Generalize the previous commit to handle hardwired misa.c.Prashanth Mundkur1-11/+19
2019-03-29Tweak legalize_xepc according to spec: xepc[1] should always be writeable.Robert Norton1-4/+5
2019-02-19Use sizeof xlen instead of the value definitions of xlen.Prashanth Mundkur1-5/+5
2019-02-13Fix a bug introduced in changing sxl/uxl handling; fix comment.Prashanth Mundkur1-2/+2
2019-02-12Start extracting bits of vmem that should be common to RV32, and add some def...Prashanth Mundkur1-12/+25
2019-02-11Fix xlen variable name.Prashanth Mundkur1-4/+4
2019-02-11Handle SXL/UXL not being present in mstatus in RV32 by using explicit getters...Prashanth Mundkur1-8/+53
2019-02-11Fix mvendorid width.Prashanth Mundkur1-1/+1
2019-02-11Parameterize CSR fields for xlen, and fix definitions for CSRs which are alwa...Prashanth Mundkur1-14/+14
2019-02-08Start parameterizing definitions by xlen, which is currently still 64.Prashanth Mundkur1-10/+10
2019-01-29Add more of the 'N' standard extension.Prashanth Mundkur1-0/+1
2019-01-29Factor the _sys functionality into separate files for architectural state and...Prashanth Mundkur1-0/+536