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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 16:59:13 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 17:19:57 -0800 |
| commit | b9cccb81930ebe51f6e13621de3d9cf67f46ee6a (patch) | |
| tree | 779f4de29808bcca972ee6a4c8e5c722f41f1dba /model/riscv_sys_regs.sail | |
| parent | 1f476139d69d25800c26db8451e3a8af68606f66 (diff) | |
| download | sail-riscv-b9cccb81930ebe51f6e13621de3d9cf67f46ee6a.zip sail-riscv-b9cccb81930ebe51f6e13621de3d9cf67f46ee6a.tar.gz sail-riscv-b9cccb81930ebe51f6e13621de3d9cf67f46ee6a.tar.bz2 | |
Fix xlen variable name.
Diffstat (limited to 'model/riscv_sys_regs.sail')
| -rw-r--r-- | model/riscv_sys_regs.sail | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 03f5520..46a2f77 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -120,13 +120,13 @@ bitfield Mstatus : xlenbits = { register mstatus : Mstatus function get_mstatus_SXL(m : Mstatus) -> arch_xlen = { - if sizeof(xlen) == 32 + if xlen == 32 then arch_to_bits(RV32) else m.bits()[35 .. 34] } function set_mstatus_SXL(m : Mstatus, a : arch_xlen) -> Mstatus = { - if sizeof(xlen) == 32 + if xlen == 32 then m else { let m = vector_update_subrange(m.bits(), 35, 34, a); @@ -135,13 +135,13 @@ function set_mstatus_SXL(m : Mstatus, a : arch_xlen) -> Mstatus = { } function get_mstatus_UXL(m : Mstatus) -> arch_xlen = { - if sizeof(xlen) == 32 + if xlen == 32 then arch_to_bits(RV32) else m.bits()[33 .. 32] } function set_mstatus_UXL(m : Mstatus, a : arch_xlen) -> Mstatus = { - if sizeof(xlen) == 32 + if xlen == 32 then m else { let m = vector_update_subrange(mstatus.bits(), 33, 32, a); |