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This is the newer, less confusing (and documented!) syntax. Fixes #425.
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This script was used to do the modification:
```
from pathlib import Path
import re
RE_LINE = r"/\*={50,150}\*/\n"
RE_MIDDLE = r"/\*.*\*/\n"
NEW_TEXT = """/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/
"""
REPLACEMENT = re.compile(rf"^{RE_LINE}(?:{RE_MIDDLE}){{10,100}}{RE_LINE}")
def main():
for file in Path("model").glob("**/*.sail"):
text = file.read_text(encoding="utf-8")
text = REPLACEMENT.sub(NEW_TEXT, text, 1)
file.write_text(text, encoding="utf-8")
if __name__ == "__main__":
main()
```
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This implements a lot of missing functionality for PMPs.
* Support 64 PMPs as well as 0 and 16.
* Support setting PMP grain
* Return correct address bits on read (some read as 0 or 1 depending on the grain and match type)
* Unlock PMPs on reset
* Implement pmpcfg WARL legalisation
Co-authored-by: Ben Fletcher <benjamin.fletcher@codasip.com>
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Use newer bitfield syntax, which has been part of Sail for
a while now. Should in theory be more efficient as it removes
a level of indirection for bitfield accesses.
It's also much more friendly to `sail -fmt`, which has no idea
how to handle the old bitfield syntax.
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Since Sail 0.15 (released Nov 2022), effects have had no effect. They now generate a deprecation warning. This commit removes all the effect annotations from the model, thus fixing the compiler warnings.
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Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
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-X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)" (#220)
Reverts #219. Merged without code review and with many issues.
This reverts commit 43b81eafc660ab584e1684668995957764a5e684.
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-X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)
* added 3 command-line switches: -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond
* example commit
* fixed some type warnings/errors (between int/bool)
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Unaligned writes or writes narrower than 32-bits are not supported.
Fixes #69.
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Rename var to make it clear it is physical and not virtual.
There are a lot of variables in riscv_mem.sail and riscv_platform.sail named addr and it's not always clear if that is physical or virtual address. These changes rename those variables to paddr to reduce ambiguity.
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E_CHERI code. Enable extensions for PTE checks and PTW errors, and propagate those into exception codes.
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divergence when using TestRIG.
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- unify AccessType and ReadType since they were essentially redundant,
making it easier to implement PMP checks for ReadWrite/atomic accesses.
- add command line options to enable PMP in the platform
- also fix the matching for the case when all entries are off
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handlers return nextPC values as opposed to setting them.
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and htif.
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Reverts 7df2149
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