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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-07-22 18:07:58 -0700
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-07-22 18:14:10 -0700
commitfb341ef48e8c6518616394da64881ec0d79fd51c (patch)
tree6e3bcae979ed14db6251e1a2ef5caff4a16f61f4 /model/riscv_platform.sail
parentbf32b39f88d88a9b5d1002b714190db5bdd2b8ec (diff)
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Make a custom exception code available for extensions, and remove the E_CHERI code. Enable extensions for PTE checks and PTW errors, and propagate those into exception codes.
Diffstat (limited to 'model/riscv_platform.sail')
-rw-r--r--model/riscv_platform.sail12
1 files changed, 6 insertions, 6 deletions
diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail
index 52511a9..dac7490 100644
--- a/model/riscv_platform.sail
+++ b/model/riscv_platform.sail
@@ -194,7 +194,7 @@ function clint_load(addr, width) = {
else {
if get_config_print_platform()
then print_platform("clint[" ^ BitStr(addr) ^ "] -> <not-mapped>");
- MemException(E_Load_Access_Fault)
+ MemException(E_Load_Access_Fault())
}
}
@@ -240,7 +240,7 @@ function clint_store(addr, width, data) = {
} else {
if get_config_print_platform()
then print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (<unmapped>)");
- MemException(E_SAMO_Access_Fault)
+ MemException(E_SAMO_Access_Fault())
}
}
@@ -285,7 +285,7 @@ function htif_load(addr, width) = {
then MemValue(sail_zero_extend(htif_tohost[31..0], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */
else if width == 4 & addr == plat_htif_tohost() + 4
then MemValue(sail_zero_extend(htif_tohost[63..32], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */
- else MemException(E_Load_Access_Fault)
+ else MemException(E_Load_Access_Fault())
}
/* The rreg,wreg effects are an artifact of using 'register' to implement device state. */
@@ -356,14 +356,14 @@ function mmio_read forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width
then clint_load(addr, width)
else if within_htif_readable(addr, width) & (1 <= 'n)
then htif_load(addr, width)
- else MemException(E_Load_Access_Fault)
+ else MemException(E_Load_Access_Fault())
function mmio_write forall 'n, 0 <'n <= max_mem_access . (addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) =
if within_clint(addr, width)
then clint_store(addr, width, data)
else if within_htif_writable(addr, width) & 'n <= 8
then htif_store(addr, width, data)
- else MemException(E_SAMO_Access_Fault)
+ else MemException(E_SAMO_Access_Fault())
/* Platform initialization and ticking. */
@@ -383,7 +383,7 @@ function handle_illegal() -> unit = {
let info = if plat_mtval_has_illegal_inst_bits ()
then Some(instbits)
else None();
- let t : sync_exception = struct { trap = E_Illegal_Instr,
+ let t : sync_exception = struct { trap = E_Illegal_Instr(),
excinfo = info,
ext = None() };
set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))