sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-07-09	Add some missed logging guards.	Prashanth Mundkur	1	-22/+41
2019-07-03	Add a maximum memory access size to slightly improve C code geneation.	Robert Norton	1	-8/+8
2019-07-01	Predicate another bit of tracing.	Robert Norton	1	-1/+2
2019-06-24	Add PMP checks to physical memory accesses.	Prashanth Mundkur	1	-0/+6
2019-05-03	Fix inconsistency in accessing PC/nextPC, which also clarifies which handlers...	Prashanth Mundkur	1	-1/+1
2019-04-24	Add extended model from cheri-merge.	Prashanth Mundkur	1	-25/+30
2019-04-17	Fix a 64-bitism.	Prashanth Mundkur	1	-1/+1
2019-03-14	Merge branch 'master' into rmem_interpreter	Jon French	1	-31/+85
2019-03-12	riscv_platform.sail: use externs for platform values even in interpreter	Jon French	1	-18/+10
2019-03-04	Add defaults for platform values for use when interpreting	Jon French	1	-1/+25
2019-02-26	Initial cleanup of the prelude, using standard prelude instead when possible.	Prashanth Mundkur	1	-14/+14
2019-02-21	Fix the ocaml platform to respect the architectural width.	Prashanth Mundkur	1	-8/+17
2019-02-11	Handle 32-bit accesses to the mmio regions and device registers of the clint ...	Prashanth Mundkur	1	-23/+68
2019-02-11	Fix xlen variable name.	Prashanth Mundkur	1	-5/+5
2019-02-11	Fix 64-bit constants.	Prashanth Mundkur	1	-3/+3
2019-02-08	Start parameterizing definitions by xlen, which is currently still 64.	Prashanth Mundkur	1	-6/+6
2019-01-25	Tweaks to reservation handling.	Prashanth Mundkur	1	-1/+1
2019-01-21	Remove temporary workaround for Lem generation	Thomas Bauereiss	1	-5/+5
2019-01-14	Reorganize directory structure.	Prashanth Mundkur	1	-0/+295