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riscv_insts_cext.sail
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Author
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2019-08-19
RISC-V spec, without implicit casts
Alasdair Armstrong
1
-2
/
+2
2019-05-10
Rename regbits to regidx, to clarify the type is an index and not the content...
Prashanth Mundkur
1
-83
/
+83
2019-05-10
Use an explicit enum to indicate the retire status as opposed to a boolean to...
Prashanth Mundkur
1
-1
/
+1
2019-05-03
Fix a todo for c.slli on RV32.
Prashanth Mundkur
1
-3
/
+2
2019-05-03
Minor formatting cleanup and remove obsolete comments.
Prashanth Mundkur
1
-9
/
+13
2019-04-09
Fix c.addiw to expand to a non-rvc instruction as per spec.
Prashanth Mundkur
1
-7
/
+2
2019-02-19
Use sizeof xlen instead of the value definitions of xlen.
Prashanth Mundkur
1
-32
/
+32
2019-02-11
Fix xlen variable name.
Prashanth Mundkur
1
-32
/
+32
2019-02-08
Add xlen guards on encdec and assembly guards, and encdec for c.jal.
Prashanth Mundkur
1
-15
/
+43
2019-01-25
Add misa checks for instructions not in the base set.
Prashanth Mundkur
1
-0
/
+5
2019-01-25
Factor out each extension into separate files, do some minor cleanup.
Prashanth Mundkur
1
-0
/
+527