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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-04-09 17:08:40 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-04-09 17:08:40 -0700 |
| commit | ef856666f5ab170fc32ff8b11d134446728d7569 (patch) | |
| tree | e63793aa721a0675acbe22951ac8ee99fa3eaa58 /model/riscv_insts_cext.sail | |
| parent | f8322738c39246be7c83bfcd3dda2344ffaf862b (diff) | |
| download | sail-riscv-ef856666f5ab170fc32ff8b11d134446728d7569.zip sail-riscv-ef856666f5ab170fc32ff8b11d134446728d7569.tar.gz sail-riscv-ef856666f5ab170fc32ff8b11d134446728d7569.tar.bz2 | |
Fix c.addiw to expand to a non-rvc instruction as per spec.
Diffstat (limited to 'model/riscv_insts_cext.sail')
| -rw-r--r-- | model/riscv_insts_cext.sail | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/model/riscv_insts_cext.sail b/model/riscv_insts_cext.sail index 70d4978..4986278 100644 --- a/model/riscv_insts_cext.sail +++ b/model/riscv_insts_cext.sail @@ -150,13 +150,8 @@ mapping clause encdec_compressed = C_ADDIW(imm5 @ imm40, rsd) <-> 0b001 @ imm5 : bits(1) @ rsd : regbits @ imm40 : bits(5) @ 0b01 if rsd != zreg & sizeof(xlen) == 64 -function clause execute (C_ADDIW(imm, rsd)) = { - let imm : bits(32) = EXTS(imm); - let rs_val = X(rsd); - let res : bits(32) = rs_val[31..0] + imm; - X(rsd) = EXTS(res); - true -} +function clause execute (C_ADDIW(imm, rsd)) = + execute(ADDIW(EXTS(imm), rsd, rsd)) mapping clause assembly = C_ADDIW(imm, rsd) if sizeof(xlen) == 64 |