sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-05-11	Change immediates to be signed in assembly	KotorinMinami	1	-10/+10
2024-03-24	Add RV32 restriction for compressed shift instructions	Tim Hutt	1	-4/+4
2024-02-08	Shorten copyright notice at the top of each file	Tim Hutt	1	-65/+3
2024-01-31	Update bitfield syntax	Alasdair	1	-1/+1
2023-11-29	Make consistent operand names	Paul A. Clarke	1	-2/+2
2023-08-01	Rename EXTZ and EXTS	Alasdair	1	-20/+20
2023-05-29	apply_headers: regenerate copyright headersupdate-copyright-headers	Philipp Tomsich	1	-1/+3
2021-07-29	Use headache to apply copyright header at request of Peter Sewell.	Robert Norton	1	-0/+68
2020-05-22	Add compressed F,D instructions.	Prashanth Mundkur	1	-2/+0
2019-08-19	RISC-V spec, without implicit casts	Alasdair Armstrong	1	-2/+2
2019-05-10	Rename regbits to regidx, to clarify the type is an index and not the content...	Prashanth Mundkur	1	-83/+83
2019-05-10	Use an explicit enum to indicate the retire status as opposed to a boolean to...	Prashanth Mundkur	1	-1/+1
2019-05-03	Fix a todo for c.slli on RV32.	Prashanth Mundkur	1	-3/+2
2019-05-03	Minor formatting cleanup and remove obsolete comments.	Prashanth Mundkur	1	-9/+13
2019-04-09	Fix c.addiw to expand to a non-rvc instruction as per spec.	Prashanth Mundkur	1	-7/+2
2019-02-19	Use sizeof xlen instead of the value definitions of xlen.	Prashanth Mundkur	1	-32/+32
2019-02-11	Fix xlen variable name.	Prashanth Mundkur	1	-32/+32
2019-02-08	Add xlen guards on encdec and assembly guards, and encdec for c.jal.	Prashanth Mundkur	1	-15/+43
2019-01-25	Add misa checks for instructions not in the base set.	Prashanth Mundkur	1	-0/+5
2019-01-25	Factor out each extension into separate files, do some minor cleanup.	Prashanth Mundkur	1	-0/+527