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This script was used to do the modification:
```
from pathlib import Path
import re
RE_LINE = r"/\*={50,150}\*/\n"
RE_MIDDLE = r"/\*.*\*/\n"
NEW_TEXT = """/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/
"""
REPLACEMENT = re.compile(rf"^{RE_LINE}(?:{RE_MIDDLE}){{10,100}}{RE_LINE}")
def main():
for file in Path("model").glob("**/*.sail"):
text = file.read_text(encoding="utf-8")
text = REPLACEMENT.sub(NEW_TEXT, text, 1)
file.write_text(text, encoding="utf-8")
if __name__ == "__main__":
main()
```
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Use newer bitfield syntax, which has been part of Sail for
a while now. Should in theory be more efficient as it removes
a level of indirection for bitfield accesses.
It's also much more friendly to `sail -fmt`, which has no idea
how to handle the old bitfield syntax.
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Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
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This reverts commit c5e62ea4b3d481fcd491b22b317cc319b089f05d.
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* Adds Zfinx enable flag
* Hardwire misa.{f,d} and mstats.FS to 0
* Moving nan boxing functions to fdext_reg
* Swaps register names for floating point instructions
Adds new mapping to swap register names, and use it in all assembly clauses
* Disable Floating point loads, stores and moves
* Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points
Changes register accessed for floating point instructions and modify nan boxing functions for zfinx
* Formatting
Remove couple of misplaced whitespace, unnecessary parens
* Fix inconsistent indentation in insts_dext file
* Fix spacing in fdext_regs
* Remove redundant comparasion with true/ false
* Constistant tuples spacing and removes couple of unnecessary parens.
* Consistent functions declaration & calls spacing and removes couple of unnecessary parens.
* Consistent spacing and removes couple of unnecessary comparasion with true/false
* Make spacing consistent
* Remove checks from execution stage
* Add checks to encdec stage
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encdec_compressed.
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Fixes #51.
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