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author | Ibrahim Abu Kharmeh <abukharmeh@gmail.com> | 2021-11-17 15:41:15 +0000 |
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committer | GitHub <noreply@github.com> | 2021-11-17 15:41:15 +0000 |
commit | c5e62ea4b3d481fcd491b22b317cc319b089f05d (patch) | |
tree | 5ddc23d7d67d434cd54b59dd8e3ae207f10fb430 /model/riscv_insts_cdext.sail | |
parent | 01720566318e292df12693bba1fe5f09ea0857df (diff) | |
download | sail-riscv-c5e62ea4b3d481fcd491b22b317cc319b089f05d.zip sail-riscv-c5e62ea4b3d481fcd491b22b317cc319b089f05d.tar.gz sail-riscv-c5e62ea4b3d481fcd491b22b317cc319b089f05d.tar.bz2 |
Initial introduction of zfinx (#75)
* Adds Zfinx enable flag
* Hardwire misa.{f,d} and mstats.FS to 0
* Moving nan boxing functions to fdext_reg
* Swaps register names for floating point instructions
Adds new mapping to swap register names, and use it in all assembly clauses
* Disable Floating point loads, stores and moves
* Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points
Changes register accessed for floating point instructions and modify nan boxing functions for zfinx
* Formatting
Remove couple of misplaced whitespace, unnecessary parens
* Fix inconsistent indentation in insts_dext file
* Fix spacing in fdext_regs
* Remove redundant comparasion with true/ false
* Constistant tuples spacing and removes couple of unnecessary parens.
* Consistent functions declaration & calls spacing and removes couple of unnecessary parens.
* Consistent spacing and removes couple of unnecessary comparasion with true/false
* Make spacing consistent
* Remove checks from execution stage
* Add checks to encdec stage
Diffstat (limited to 'model/riscv_insts_cdext.sail')
-rw-r--r-- | model/riscv_insts_cdext.sail | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/model/riscv_insts_cdext.sail b/model/riscv_insts_cdext.sail index 77a6302..0c6bbd1 100644 --- a/model/riscv_insts_cdext.sail +++ b/model/riscv_insts_cdext.sail @@ -77,9 +77,9 @@ union clause ast = C_FLDSP : (bits(6), regidx) mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) <-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10 - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) function clause execute (C_FLDSP(uimm, rd)) = { let imm : bits(12) = EXTZ(uimm @ 0b000); @@ -95,9 +95,9 @@ mapping clause assembly = C_FLDSP(uimm, rd) union clause ast = C_FSDSP : (bits(6), regidx) mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) <-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10 - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) function clause execute (C_FSDSP(uimm, rs2)) = { let imm : bits(12) = EXTZ(uimm @ 0b000); @@ -113,9 +113,9 @@ mapping clause assembly = C_FSDSP(uimm, rs2) union clause ast = C_FLD : (bits(5), cregidx, cregidx) mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) <-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00 - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) function clause execute (C_FLD(uimm, rsc, rdc)) = { let imm : bits(12) = EXTZ(uimm @ 0b000); @@ -133,9 +133,9 @@ mapping clause assembly = C_FLD(uimm, rsc, rdc) union clause ast = C_FSD : (bits(5), cregidx, cregidx) mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) <-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00 - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() & ~ (sys_enable_zfinx()) function clause execute (C_FSD(uimm, rsc1, rsc2)) = { let imm : bits(12) = EXTZ(uimm @ 0b000); |